Milestone-Proposal:First RISC Microprocessor
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This Proposal has been approved, and is now a Milestone
To the proposer’s knowledge, is this achievement subject to litigation?
Is the achievement you are proposing more than 25 years old? Yes
Is the achievement you are proposing within IEEE’s designated fields as defined by IEEE Bylaw I-104.11, namely: Engineering, Computer Sciences and Information Technology, Physical Sciences, Biological and Medical Sciences, Mathematics, Technical Communications, Education, Management, and Law and Policy. Yes
Did the achievement provide a meaningful benefit for humanity? Yes
Was it of at least regional importance? Yes
Has an IEEE Organizational Unit agreed to pay for the milestone plaque(s)? Yes
Has an IEEE Organizational Unit agreed to arrange the dedication ceremony? Yes
Has the IEEE Section in which the milestone is located agreed to take responsibility for the plaque after it is dedicated? Yes
Has the owner of the site agreed to have it designated as an IEEE Milestone? Yes
Year or range of years in which the achievement occurred:
Title of the proposed milestone:
First RISC Microprocessor 1980-82
Plaque citation summarizing the achievement and its significance:
UC Berkeley students designed and implemented the first VLSI reduced instruction set computer in 1981. The simplified instructions of RISC-I reduced the hardware for instruction decode and control, which enabled a flat 32-bit address space, a large set of registers, and pipelined execution. A good match to C programs and the Unix operating system, RISC-I influenced instruction sets widely used today, including those for game consoles, smartphones and tablets.
In what IEEE section(s) does it reside?
Oakland East Bay Section
IEEE Organizational Unit(s) which have agreed to sponsor the Milestone:
IEEE Organizational Unit(s) paying for milestone plaque(s):
Unit: Oakland-East Bay Section
Senior Officer Name: Kate Jenkins
IEEE Organizational Unit(s) arranging the dedication ceremony:
Unit: Oakland-East Bay Section
Senior Officer Name: Catherine Jenkins, Chair
IEEE section(s) monitoring the plaque(s):
IEEE Section: Oakland-East Bay Section
IEEE Section Chair name: Catherine Jenkins
Proposer name: David A. Hodges
Proposer email: Proposer's email masked to public
Please note: your email address and contact information will be masked on the website for privacy reasons. Only IEEE History Center Staff will be able to view the email address.
Street address(es) and GPS coordinates of the intended milestone plaque site(s):
NW corner of Hearst Ave. and LeRoy Ave., Berkeley CA 94720 37*52'32.67" N 122*15'31.44" W elev. 414 ft.
Describe briefly the intended site(s) of the milestone plaque(s). The intended site(s) must have a direct connection with the achievement (e.g. where developed, invented, tested, demonstrated, installed, or operated, etc.). A museum where a device or example of the technology is displayed, or the university where the inventor studied, are not, in themselves, sufficient connection for a milestone plaque.
Please give the address(es) of the plaque site(s) (GPS coordinates if you have them). Also please give the details of the mounting, i.e. on the outside of the building, in the ground floor entrance hall, on a plinth on the grounds, etc. If visitors to the plaque site will need to go through security, or make an appointment, please give the contact information visitors will need. Soda Hall has been the permanent the home for Computer Science at Berkeley since it was completed in 1996. The 1980-82 work for "First RISC Microprocessor" was conducted in several other buildings, before there was a designated building for Computer Science.
Are the original buildings extant?
Some of them, but it's clear that Soda Hall is the best place for this Milestone.
Details of the plaque mounting:
Mounting will be indoors on a wall in the public lobby/reception area just outside the main Auditorium in Soda Hall.
How is the site protected/secured, and in what ways is it accessible to the public?
Soda Hall is open to the public 8-6 5 days per week, excepting holidays. Building security is provided by the University of California Police.
Who is the present owner of the site(s)?
Regents of the University of California
What is the historical significance of the work (its technological, scientific, or social importance)?
In the 1970s, the general trend in in computer design was to increase the complexity of computer architectures. The thought was that this would best exploit the rapidly advancing capabilities of semiconductor technology. The popular DEC VAX 11-780 was the leading example. About 280 machine-language instructions were implemented in the VAX hardware. The VAX 11-780, a so-called super minicomputer, was advertised as exercising 1 million instructions/second and sold for about $100,000. This class of computers was then termed CISCs, or complex instruction set computers.
Professors David Patterson and Carlo Sequin of the University of California at Berkeley observed that compilers for high-level computer languages, such as C, rarely utilized the added instructions. They thought that overall performance could be improved by optimizing the combination of processor function and memory on a single chip. Better overall performance at a much lower cost might be achieved by simplifying the processor, thereby allowing more chip area to be devoted to memory. Thus the goal was defined as a RISC, or reduced instruction set computer.
The RISC-I project was initiated in 1980 with assignments in a sequence of graduate classes at Berkeley, aiming to validate the RISC hypothesis. Initial conclusions based on simulation were positive, so the project continued, with critical grant support from DARPA. Students designed a processor with just 31 instructions, each executed in a single clock cycle. Included on the same student-designed chip, were 78 32-bit registers. This was enough memory to enable one-cycle execution of a large fraction of the instructions in compiled code.
Early in the project, the Berkeley team learned of previously unpublished work at IBM around 1975, led by Dr. John Cocke. The IBM 801, never commercialized, pioneered architectural principles similar to those independently chosen by the Berkeley team, though the goals for the 801 were quite different. Dr. Cocke visited Berkeley in 1981 and spoke to the student-faculty team. He gave them enthusiastic encouragement for their undertaking.
The first student-designed RISC-I chips, realized via the DARPA and NSF-funded MOSIS implementation service, were received in the fall of 1981. They were functional, though with minor deficiencies. However, performance was sufficient to convince previous skeptics to recognize the merits of the RISC approach to design of very large scale integrated (VLSI) computing. After correction of minor design bugs, the RISC-I design proved to outperform the VAX on almost every real-world benchmark.
No patents for the RISC-I design were sought for the Berkeley project. The earlier design of the IBM 801 might have been an impediment, though it had not been publicly disclosed. But the Berkeley team, funded primarily by government agencies, admirably chose to place their results in the public domain. This decision proved to be important to the later widespread adoption of the basic RISC concepts.
The RISC design was first commercialized as the SPARC microprocessor, introduced in 1987. Professor Patterson served as a consultant to Sun Microsystems, assisting Sun in development of the powerful RISC-based SPARC workstations. The SPARC workstations became a leading tool in the design of integrated circuits. Sun is now a part of the Oracle Corporation.
A similar project was carried on at about the same time at Stanford University, led by Professor John Hennessey. Professors Hennessey and Patterson are long-term friends and collaborators. They are co-authors of the leading textbook on computer architecture. The Stanford project produced a similar RISC processor design, termed MIPS. Also, there were important improvements to the compiler. The MIPS design was successfully commercialized by MIPS Computer Systems, founded by Professor Hennessey and others. That company subsequently was acquired by Silicon Graphics, Inc. The MIPS architecture is widely produced for a range of applications, under license from the company.
Along another path, Advanced RISC Machines (ARM) in the UK developed a continuing series of VLSI RISC processor designs that now are produced under license by leading semiconductor manufacturers of chips for use in game consoles, smart phones, and tablet computers. You may well be carrying one of these products today.
Not to be overlooked, the academic projects at Berkeley and Stanford educated scores of creative and talented Master’s degree and Doctoral students who became the next generation of technology leaders.
What obstacles (technical, political, geographic) needed to be overcome?
The largest obstacle in 1980 was skepticism among knowledgeable professionals, friendly or otherwise. No one on the team had prior experience designing VLSI computer processor chips. Professors Patterson and Sequin had the courage to continue. Of course, the work would not have been possible without the major support of DARPA and MOSIS.
What features set this work apart from similar achievements?
The IBM work begun in 1975, led by Dr. John Cocke, was aimed the control requirements for an electronic telephone central switch. That project influenced by Dr. Cocke’s recognition that compilers of that era rarely made use of complex high-level language instructions. A working model was built with off-the-shelf emitter-coupled logic (ECL) chips. There was no recognition of the benefit of combining many fast registers on the same chip as the central processor, and no attention to the possibility of an inexpensive single-chip microprocessor.
The MIPS project, led by Prof. John Hennessey at Stanford, featured important attention to the role of the compiler in making best use of RISC processor resources. The first working chip resulting from that project came about a year after RISC-I at Berkeley.
Supporting texts and citations to establish the dates, location, and importance of the achievement: Minimum of five (5), but as many as needed to support the milestone, such as patents, contemporary newspaper articles, journal articles, or chapters in scholarly books. 'Scholarly' is defined as peer-reviewed, with references, and published. You must supply the texts or excerpts themselves, not just the references. At least one of the references must be from a scholarly book or journal article. All supporting materials must be in English, or accompanied by an English translation.
Patterson, David A., and David R. Ditzel, "The case for the reduced instruction set computer." ACM SIGARCH Computer Architecture News 8.6 (1980): 25-33.
Patterson, David A., and Carlo H. Sequin, "RISC I: A reduced instruction set VLSI computer." Proceedings of the 8th annual symposium on Computer Architecture, IEEE Computer Society Press, 1981. Patterson, David A., and Carlo H. Sequin, “Design and Implementation of RISC I” UC Berkeley EECS Technical Report CSD-82-106, 1982. (Also appeared in Proc. Advanced Course on VLSI Architecture, University of Bristol, England, July 19-30, 1982.)
Patterson, David A., and Carlo H. Sequin, "A VLSI RISC." IEEE computer 15.9 (1982): 8-21. Digital Object Identifier: 10.1109/MC.1982.1654133
Sherburne, R. W., Katevenis, M. G., Patterson, D. A., & Sequin, C. H. (1984), “A 32-bit NMOS microprocessor with a large register file,” Solid-State Circuits, IEEE Journal of,19(5), 682-689. Digital Object Identifier: 10.1109/JSSC.1984.1052208
Patterson, David A. "Reduced instruction set computers." Communications of the ACM 28.1 (1985): 8-21.
Supporting materials (supported formats: GIF, JPEG, PNG, PDF, DOC): All supporting materials must be in English, or if not in English, accompanied by an English translation. You must supply the texts or excerpts themselves, not just the references. For documents that are copyright-encumbered, or which you do not have rights to post, email the documents themselves to email@example.com. Please see the Milestone Program Guidelines for more information.
RISC1.jpeg (chip photo) Dave&Carlo.jpg RISC1group.jpg RISCCAD.jpg (3 photos of people)
I have uploaded these, with captions. None is copyrighted.
Please email a jpeg or PDF a letter in English, or with English translation, from the site owner(s) giving permission to place IEEE milestone plaque on the property, and a letter (or forwarded email) from the appropriate Section Chair supporting the Milestone application to firstname.lastname@example.org with the subject line "Attention: Milestone Administrator." Note that there are multiple texts of the letter depending on whether an IEEE organizational unit other than the section will be paying for the plaque(s).