File:Boolean-logic-by-parametron-and-full-adder.JPG
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Summary
Circuit diagram of paremetron logic Taken from Committee for the 50th Anniversary of PC-1, "パラメトロン計算機 PC-1 1958-2008" (Parametron Computer PC-1 1958-2008 in Japanese), https://www.iijlab.net/~ew/pc1/pc150th.pdf), Figure 5, page 34.
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| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 00:12, 18 April 2025 | | 1,728 × 886 (115 KB) | Zephyrus00jp (talk | contribs) | Circuit diagram of paremetron logic Taken from Committee for the 50th Anniversary of PC-1, "パラメトロン計算機 PC-1 1958-2008" (Parametron Computer PC-1 1958-2008 in Japanese), https://www.iijlab.net/~ew/pc1/pc150th.pdf), Figure 5, page 34. |
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