Milestone-Proposal:Development of the Field Programmable Gate Array
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Docket #:2021-02
This is a draft proposal, that has not yet been submitted. To submit this proposal, click on the edit button in toolbar above, indicated by an icon displaying a pencil on paper. At the bottom of the form, check the box that says "Submit this proposal to the IEEE History Committee for review. Only check this when the proposal is finished" and save the page.
To the proposer’s knowledge, is this achievement subject to litigation? No
Is the achievement you are proposing more than 25 years old? Yes
Is the achievement you are proposing within IEEE’s designated fields as defined by IEEE Bylaw I-104.11, namely: Engineering, Computer Sciences and Information Technology, Physical Sciences, Biological and Medical Sciences, Mathematics, Technical Communications, Education, Management, and Law and Policy. Yes
Did the achievement provide a meaningful benefit for humanity? Yes
Was it of at least regional importance? Yes
Has an IEEE Organizational Unit agreed to pay for the milestone plaque(s)? Yes
Has the IEEE Section(s) in which the plaque(s) will be located agreed to arrange the dedication ceremony? Yes
Has the IEEE Section in which the milestone is located agreed to take responsibility for the plaque after it is dedicated? Yes
Has the owner of the site agreed to have it designated as an IEEE Milestone? Yes
Year or range of years in which the achievement occurred:
1984
Title of the proposed milestone:
The Field Programmable Gate Array (FPGA), 1984
Plaque citation summarizing the achievement and its significance; if personal name(s) are included, such name(s) must follow the achievement itself in the citation wording: Text absolutely limited by plaque dimensions to 70 words; 60 is preferable for aesthetic reasons.
The FPGA was an integrated circuit in which Boolean logic functions and interconnects were programmed by the user. Xilinx, co-founded by Ross Freeman to productize his 1984 invention, introduced the XC2064 in 1985 with 64 programmable 4-input logic functions. Xilinx’s FPGAs helped accelerate a dramatic industry shift: "fabless” companies could use software tools to design hardware while engaging "foundry" companies to handle the capital-intensive task of manufacturing the hardware.
200-250 word abstract describing the significance of the technical achievement being proposed, the person(s) involved, historical context, humanitarian and social impact, as well as any possible controversies the advocate might need to review.
In the early 1980s, custom integrated circuits, commonly called Application Specific ICs (ASICs), were available from many companies, and were supported by the nascent Electronic Design Automation (EDA) industry. Programmable Logic Devices (PLDs) were pre-manufactured devices with a simple fixed architecture, and which were programmable with simple software. However, PLDs scaled poorly with process technology, both in area and performance.
The Field Programmable Gate Array (FPGA), with both programmable and reprogrammable logic and interconnect, made significant advances over the PLD. The programmable interconnect enabled the FPGA to scale with process technology scaling (in sync with Moore’s Law), albeit at the cost of ASIC-like placement and routing to fit a design into the FPGA. FPGA vendors were forced to write their own physical EDA software, competing not only against ASIC and PLD companies, but also against the EDA industry.
The innovation to program FPGAs by writing on-chip memory cells relieved the requirement that the devices use EEPROM or antifuse technology, at the cost of many more transistors. However, since FPGAs scaled with process technology, that cost faded over time. Significantly, FPGAs were able to leverage advanced process nodes early. Their process technology advantage mitigated their transistor count disadvantage.
FPGAs grew in complexity over the years, adding memory, arithmetic, high-speed I/O transceivers, cryptography, analog interfaces, and microprocessors to their logic components. As a result, FPGAs opened up access to advanced process technology to many more designers than ASIC companies could. This access permitted FPGAs to be deployed in advanced applications, including early internet routers and AI/ML hardware.
IEEE technical societies and technical councils within whose fields of interest the Milestone proposal resides.
• Computer Society (CS)
• Circuits & Systems (CAS) Society
• Solid-State Circuits Society (SSCS)
In what IEEE section(s) does it reside?
Santa Clara Valley Section
IEEE Organizational Unit(s) which have agreed to sponsor the Milestone:
IEEE Organizational Unit(s) paying for milestone plaque(s):
Unit: Santa Clara Valley Section
Senior Officer Name: Taylor Winship
IEEE Organizational Unit(s) arranging the dedication ceremony:
Unit: Santa Clara Valley Section
Senior Officer Name: Taylor Winship
IEEE section(s) monitoring the plaque(s):
IEEE Section: Santa Clara Valley Section
IEEE Section Chair name: Taylor Winship
Milestone proposer(s):
Proposer name: Brian Berg
Proposer email: Proposer's email masked to public
Please note: your email address and contact information will be masked on the website for privacy reasons. Only IEEE History Center Staff will be able to view the email address.
Street address(es) and GPS coordinates in decimal form of the intended milestone plaque site(s):
2100 Logic Dr, Bldg. 4, San Jose, CA 95124 US (37.25300, -121.93625)
Describe briefly the intended site(s) of the milestone plaque(s). The intended site(s) must have a direct connection with the achievement (e.g. where developed, invented, tested, demonstrated, installed, or operated, etc.). A museum where a device or example of the technology is displayed, or the university where the inventor studied, are not, in themselves, sufficient connection for a milestone plaque.
Please give the address(es) of the plaque site(s) (GPS coordinates if you have them). Also please give the details of the mounting, i.e. on the outside of the building, in the ground floor entrance hall, on a plinth on the grounds, etc. If visitors to the plaque site will need to go through security, or make an appointment, please give the contact information visitors will need. On a pedestal stand in a glass display case in the AMD San Jose Building 4 Main Lobby.
Are the original buildings extant?
Yes.
Details of the plaque mounting:
On a pedestal stand in a glass display case in the AMD San Jose Building 4 Main Lobby.
How is the site protected/secured, and in what ways is it accessible to the public?
Accessible to the public from 7am-7pm, Monday-Friday, except holidays; otherwise it is locked, with Security patrols.
Who is the present owner of the site(s)?
Salil Raje, SVP & GM, Adaptive & Embedded Computing Group (AECG)
What is the historical significance of the work (its technological, scientific, or social importance)? If personal names are included in citation, include detailed support at the end of this section preceded by "Justification for Inclusion of Name(s)". (see section 6 of Milestone Guidelines)
FPGAs gave access to leading-edge semiconductor technology for vastly more designers than ASIC (Application-Specific Integrated Circuit) technology could provide. The ASIC design process was long and complex, requiring expertise from process technology, systems design, packaging, and test program development. As ASIC vendors could not provide sufficient assistance for a large number of customers, small customers were often turned away.
The costly mask tooling required for an ASIC design was an expense that was borne up-front, months before the device could be used in a system, and as such it was prohibitive for many potential customers. The FPGA eliminated this expense altogether. Also, while an ASIC design could become obsolete during its lengthy manufacturing cycle, FPGAs eliminated the time-lag from completion of the design until the manufacturing cycle was complete. Hardware updates to FPGAs could even be performed in the field, just like software updates. Around the time of the FPGA invention, it was estimated that only about one-third of ASIC designs survived to go into production despite the up-front non-recurring engineering (NRE) and design investment.
As such, because of their immediate availability and flexibility, FPGAs became the implementation of choice for emerging standards and computation, and they quickly began to alter the economic model of the semiconductor industry. They accelerated development of a broad range of applications, including ASIC emulation, network routers, PCI and other interface standards, and AI/ML algorithms.
Even with sophisticated Electronic Design Automation (EDA) software, large semiconductor devices are difficult to design as they require a broad range of skills in system design, logic design, circuit design, transistor-level modeling, test program generation, package design, and signal integrity. By providing a pre-manufactured device, FPGAs eliminated whole classes of problems for their users, and thus facilitated the deployment of custom silicon in a broad range of applications.
Simultaneously with FPGA device definition and product development, FPGA companies pioneered the “fabless” semiconductor company, thereby avoiding the enormous capital investment required to construct a semiconductor manufacturing facility. Instead, they enlisted semiconductor manufacturers to become “foundries” to build the FPGA device. Both models – the “fabless” semiconductor company and the manufacturing "foundry" – eventually became commonplace, and both were non-existent before the FPGA's invention.
Justification for Inclusion of Name(s) Ross Freeman is cited as the inventor of the FPGA by the National Inventors Hall of Fame [1] [1a], which cites him as the sole inventor on US Patent 4,870,302 [2] with priority date March 12, 1984, and which sets forth his FPGA invention. In 1984, Freeman co-founded Xilinx, Inc., in San Jose, CA, along with Bernard Vonderschmitt and James V Barnett II. Freeman was the FPGA inventor and CTO, Vonderschmitt was the CEO, and Barnett was the Operations person. Freeman's genius enabled him to see past the technological limitations of the day. There were dozens of ASIC companies at the time of his FPGA invention, and the successful ones were delivering what was then the fastest, lowest cost, and highest-capacity devices. The first FPGA was the Xilinx XC2064 [3] [9], which was released in 1985. Although this and all of the earliest FPGAs were slow, expensive, and low-capacity compared to then-available mask-programmed devices, Freeman understood that Moore's Law and process scaling would address these drawbacks. His FPGA invention was an architecture that was able to leverage scaling to deliver what would become a fast, inexpensive, and high-capacity device that dramatically affected the entire semiconductor industry. [18]
What obstacles (technical, political, geographic) needed to be overcome?
Limited Process Capability
When Xilinx introduced the first FPGA in 1985, the semiconductor technology available at that time was barely able to provide enough transistors on a chip for creation of a simple FPGA. As such, the initial obstacle was the definition of an architecture that was efficient and yet capable enough in capacity and performance to provide useful functionality.
Capacity, Cost, and Performance
In the intense competition of the ASIC industry of the 1980s, critical device specifications were device capacity, cost per gate, and performance. Because of the overhead of the transistors needed to enable programmability, FPGAs were significantly inferior to mask-programmed ASICs regarding all three of these parameters. The overhead of field programmability cost an estimated 10x increase in area [15], resulting in a 10x increase in cost and an associated increase in delay time. As such, these drawbacks would have seemed to make FPGAs laughably impractical.
Two key factors made FPGAs very attractive for these applications: (1) being just good enough for many applications [11], and (2) most importantly being available immediately after being programmed. As process technology improved, FPGAs grew in capacity and performance, and costs started falling. As a result, FPGAs became popular for an ever-growing set of applications [7].
Instant availability, instead of a months-long IC manufacturing cycle, was critical for many applications as well. This was particularly true since it has always been the case that (1) many chip designs contain errors, and (2) end-customer requirements frequently change in the intervening months. As such, the ability to modify or upgrade a design was very critical, and the FPGA's reprogrammability satisfied this criticality.
Electronic Design Automation (EDA)
Prior to FPGAs, the well-established EDA industry had sophisticated software, hardware, and services which enabled the design, verification, and manufacture of semiconductor devices such as programmable logic devices (PLDs) and Application-Specific Integrated Circuits (ASICs). However, the architecture of FPGAs had very different requirements.
PLD mapping was performed by a limited number of EDA companies, and they each used a standard architecture. Device vendors didn't need to develop any software - they simply ensured that they could support the mapping dictated by their EDA vendors. A semiconductor maker could become a PLD vendor merely by manufacturing silicon.
However, as the architecture of an efficient FPGA was unlike that of cell-based ASICs or gate arrays, commercial EDA in 1985 was unsuitable for their production. As FPGA logic blocks were unlike the gates in gate arrays or cell-based designs, commercial synthesis performed poorly. Similarly, commercial placement and routing technology at that time did not consider the uniqueness of the switch-like constraints of FPGA programmable routing. As a result, commercial EDA vendors were initially unwilling to modify their tools for FPGAs because of their low market penetration and low revenue.
Xilinx’s early success in the 1980s attracted others to offer the FPGA devices, promoting different architecture and different process technology. FPGA vendors were trying to sell a product with low up-front cost. However, as EDA software cost hundreds of thousands of dollars, that advantage disappeared. FPGA vendors thus had to implement their own tools for synthesis, placement, and routing. As a result, FPGA vendors competed against not only ASIC and PLD companies, but also against the entire EDA industry.
The Advantage of Owning EDA
A significant advantage that FPGA vendors gained from building their own tools was that they were able to innovate their architectures continually, while PLD vendors were dependent on their PLD software suppliers. If a PLD vendor invented an improved device, they needed to convince their software supplier to augment their software to support it. Those suppliers were reluctant to do so unless multiple vendors needed the change. As a result, PLDs were commoditized, innovations were late coming to market, and multiple vendors competed on cost. This led to innovation stagnating, and product improvements languishing.
In contrast, FPGA vendors owned their EDA. If they found an innovation in logic, interconnect, or architecture [10] [11], they could modify their own EDA to immediately support it. As a result, innovation flourished and product improvement accelerated. FPGA vendors thereby improved the quality of their FPGAs, not only in improved logic and interconnect architecture, but also with the inclusion of additional functionality beyond simple logic: memory, arithmetic, analog interfaces, high-speed I/O, and even microprocessors.
The Fabless Semiconductor Model [4], [5], [12], [13]
A further innovation in the FPGA business was a near industry-wide decision to eschew building wafer fabrication facilities (“fabs”) and instead contract with other companies to manufacture their silicon. This dramatic shift led to the Fabless Semiconductor Model wherein fabless companies would focus on design, innovation, and marketing while benefiting from the ever-advancing manufacturing capabilities of semiconductor foundry companies.
By the 1980s, it was clear that although semiconductor manufacturing was improving exponentially, so was the cost of the manufacturing facility. By using this model, FPGA vendors avoided the enormous capital expense of building and maintaining a fab.
ASIC semiconductor manufacturers always had to hustle to keep their fabs full as their equipment depreciated rapidly. Their focus was less on serving end customers and more on booking business of any kind. As small semiconductor companies could not fill a fab, they were also able to follow this model so that they could focus on their customers rather than maintaining a manufacturing facility.
Silicon foundries existed as far back as the 1980s [6]. ASIC companies of the 1980s were operating as foundries, although they considered their customers to be “system houses” rather than “fabless semiconductor companies,” which would have made them competitors.
Significant issues in the early years of this new model included deciding what information would a foundry allow a fabless company to know as detailed knowledge of design rules was essential to produce leading-edge chips. However, that information was considered to be “crown jewels” by a foundry. In addition, as a foundry needed to understand what they were building so that they could understand how to optimize manufacturing, details of a fabless company’s circuits were needed by a foundry – but these were considered to be “crown jewels” by the fabless company. As a result, close relationships were established wherein engineers on both sides bared their technology. Long before foundry-written handoffs were in place, this fabless business model ran on handshakes of executives on each side, and so mutual trust was essential. As foundries expanded globally, so did the FPGA supply chain.
One drawback of being fabless was the concept of “stacked margin.” Both the fabless FPGA vendor and the foundry needed to turn a profit. Efficiency of manufacture continued to be key. These discussions could require concessions on both sides. The fabless model allowed FPGA vendors to select and re-select their vendors, with multiple advantages. Competition could yield favorable pricing. An unreliable vendor could be side-stepped. An FPGA vendor could improve performance, for example, by booking business with a foundry that had a faster process.
The Fabless Semiconductor Association (FSA)
In 1994, Jodi Shelton and a half a dozen CEOs of fabless companies established the Fabless Semiconductor Association (FSA) in order to help nurture and shepherd the rise of the fabless semiconductor model, as well as to promote this model globally. These companies wanted to provide a cumulative and unified voice for their interests at a time when fabless companies were mostly small and unrepresented. [12], [17] The founding members were from companies including Xilinx, LSI Logic, Texas Instruments, and Motorola.
While the Semiconductor Industry Association (SIA) was considered the “voice of the U.S. semiconductor industry” when the FSA was founded in 1994, it did not allow fabless companies to be part of its leadership.
The Global Semiconductor Alliance (GSA)
In December 2007, the FSA transitioned to the Global Semiconductor Alliance (GSA) to reflect the global role that the member companies played, and to collaborate with other organizations to co-host international events. [16] As of 2025, the GSA represented over 300 corporate members that represent over 80% of the $620 billion worldwide semiconductor industry. [17] Dr. Willem "Wim" Roelandts, who was CEO of Xilinx Inc. from January 1996 to January 2008, served as GSA Chairman for a period starting with its 2007 transition from the FSA.
"The Field Programmable Gate Array (FPGA) Market size was valued at USD 12.1 billion in 2024 and is projected to reach USD 25.8 billion by 2029, growing a CAGR of 16.4% during the forecast period from 2024 to 2029." [19]
Other Companies That Benefiited from the Fabless Semiconductor Model
Chips and Technologies, Inc. (C&T), was an early fabless semiconductor company founded in Milpitas, California, in December 1984 by Gordon A. Campbell and Dado Banatao. Its first product, announced September 1985, was a four chip EGA chipset that handled the functions of 19 of IBM's proprietary chips on the Enhanced Graphics Adapter. [14] Like Xilinx, C&T was founded in 1984. Xilinx's first product was shipped in 1985, and C&T announced its first product that same year.
The FPGA's Benefit to the Foundries
FPGAs provided a benefit to the foundry that was not apparent at the outset. FPGAs became process drivers as chips that were run in the fab could be used to diagnose and improve the process itself. Previously, foundries preferred to use memory devices for this function as memories had a very regular structure and so could be easily diagnosed. This contrasted with ASIC devices which had a varied structures, and which had been more common at the foundries. As FPGAs comprised regular structures as was the case with memory devices, they were easy to diagnose.
FPGA Families
An FPGA was not a single device, but a family of devices across a range of logic and I/O capabilities. As FPGA families were produced with a large die, they served as an excellent stress test on the process, and importantly were sellable and not just a test structure. As soon as a foundry could yield them, they were money makers.
As FPGAs are made up of an array of identical logic and interconnect blocks, it was quickly discovered that they could use identical blocks in a variety of array sizes, similar to how memory makers delivered families of memories. Further, FPGAs could scale quickly with new manufacturing processes available with process scaling. This scaling of course was not simple replication, but it was much easier than developing a whole new device.
What features set this work apart from similar achievements?
FPGAs provided a significant advantage over mask-programmed custom logic: first, by being immediately available as there was no need to wait through a lengthy fabrication cycle; and second, by eliminating whole classes of engineering required to deliver a product. These classes included detailed circuit design, test program development, and packaging design. The fundamental improvement of FPGA was programmable interconnect. [7]
Programmable logic, such as the popular Programmable Logic Device (PLD), and other variants, existed before the FPGA. The architecture of those devices used circuits and structures from Programmable Read-Only Memories (PROM) to construct arrays of large fan-in AND-OR gates which made them easy to manufacture, and which permitted simple software for processing logic circuits into AND-OR programming for the devices.
The drawback of Programmable Logic Devices was in logic scaling. The size of the AND-plane of PLDs grew with the product of the number of I/O pins and the number of internal signals. The die-spanning interconnect increased resistance and capacitance on those internal signals, increasing delay and power consumption. Clever circuits delayed the well-understood day of reckoning for this architecture.
The famous Moore’s Law technology scaling was doubling the number of available transistors every two years. PLD scaling could not leverage the process scaling forever.
FPGAs included programmable logic, and most importantly, programmable interconnect. Wiring for an individual logic function did not span the entire width of the die, but only the distance to the next function. Multi-level logic was standard. Size, delay, and power of FPGA logic was not scaling with the number of I/O or internal signals. While it's true that additional interconnect was required as devices became larger, the amount of interconnect scaled more slowly than the number of logic blocks. [8] [7]
PLD architecture was limited to dozens of logic functions, and hundreds of gates of equivalent logic. In contrast, FPGA's programmable interconnect permitted semiconductor process scaling to millions of gates.
Indeed, further work to scale up PLD architecture introduced programmable interconnect. Programmable interconnect enabled the inclusion of additional types of logic blocks over time, including memory, arithmetic, ADC, transceivers, microprocessors, and AI/ML fabric.
The second significant insight was the elimination of non-volatile memory. Programmable logic was built with one-bit lookup tables to hold the truth table of the function. While some of the programmable interconnect was built with multiplexers controlled by memory cells, the bulk of it was made up of programmable interconnect points (PIPs) which were basically pass transistors controlled by static memory cells. These pass transistors are described in the 4,870,302 patent [2] at 8:31-10:68, and are illustrated in Figures 7B and 9A-G.
Though it seemed woefully inefficient to implement a single logic gate using more than a dozen memory cells, and to route signals using dozens more - where previously there had been a metal wire or a single programmed bit - this innovation further enabled FPGAs to take advantage of process technology scaling.
FPGAs programmed using SRAM-style memory cells were able to leverage the most advanced process nodes as soon as they were available. A non-volatile process module, such as antifuse or eFuse, delayed utilization of advanced nodes for many years. SRAM FPGAs continued to advance with Moore’s Law while other technologies slowed [7].
FPGAs replaced memories as process drivers for logic processes, accelerating the development of new nodes.
Why was the achievement successful and impactful?
Beyond the usual requirement of a huge amount of hard work, FPGAs were successful because:
• FPGAs have been used for a multitude of applications, including healthcare and medical devices [20], radio astronomy [21], scientific high-performance computing (HPC) applications [22], and cryptography [23].
• The novel architecture allowed FPGA capacity, performance and power to scale with process technology advances. Since the invention of the FPGA, device capacity has grown more than a million-fold, and FPGA capacity has grown similarly. [7]
• Fundamental questions in device architecture for the logic block and its interconnect network were resolved in a way that were efficient in implementation, and delivered good specification numbers.
• FPGAs were not simply a semiconductor device. FPGA offerings included EDA software and intellectual property (IP) to enable users to use the device. The FPGA, with its EDA and IP, comprised a computation solution that was analogous to a computer made up of a microprocessor, compiler and libraries. This combination enabled deployment of FPGAs in high-performance communications and computation, leading to their inclusion in early high-througput internet routers, mobile telephony DSP, and data centers for performing database operations and AI/ML.
• A major part of the FPGA value proposition was the low Non-Recurring Engineering (NRE) costs compared to the ASIC. These costs included manufacturing tooling and expensive EDA tools, and also included the months-long integrated circuit custom manufacturing cycle. FPGA users avoided these up-front costs and delays to building systems.
Supporting texts and citations to establish the dates, location, and importance of the achievement: Minimum of five (5), but as many as needed to support the milestone, such as patents, contemporary newspaper articles, journal articles, or chapters in scholarly books. 'Scholarly' is defined as peer-reviewed, with references, and published. You must supply the texts or excerpts themselves, not just the references. At least one of the references must be from a scholarly book or journal article. All supporting materials must be in English, or accompanied by an English translation.
[1] National Inventors Hall of Fame: Ross Freeman for the Field Programmable Gate Array (FPGA)
[1a] US Patent & Trademark Office Recognizes National Inventors Hall of Fame 2009 Inductees
[2] US 4,870,302 FPGA Patented Invention; Inventor: Ross H. Freeman; Priority Date: March 12, 1984
[3] Chip Hall of Fame: Xilinx XC2064 FPGA IEEE Spectrum: 30 June 2017
[4] “It’s an FPGA!”, P. Alfke, I Bolsens, B. Carter, M. Santarini, S. Trimberger; IEEE Solid-State Circuits Magazine, v3 n4, Fall 2011 (not a document link)
[5] Interview with Bernard Vonderschmitt (28 April 1995) Silicon Genesis Oral Histories of Semiconductor Technology - Host: Rob Walker, Stanford University
[6] MOSIS (Metal Oxide Semiconductor Implementation Service) Wikipedia page
[7] “Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology”, S. Trimberger, Proceedings of the IEEE, v103 n3, 15 April 2015 (not a document link)
[8] Heller-Donath Rent's Rule Wikipedia page for a rule pertaining to the organization of computing logic, specifically the relationship between the number of external signal connections to a logic block
[9] “A User-Programmable Reconfigurable Logic Array”, W. Carter, K. Duong, R.H. Freeman, H.C. Hsieh, J.Y. Ja, J.E. Mahoney, L.T. Ngo, S.L. Sze (all of Xilinx); IEEE 1986 Custom Integrated Circuits Conference
[10] “A Second Generation User-Programmable Gate Array”, H.C. Hsieh, K. Duong, J.Y. Ja, R. Kanazawa, L.T. Ngo, L.G. Tinkey, W.S. Carter, R.H. Freeman (all of Xilinx); IEEE 1987 Custom Integrated Circuits Conference
[11] "A Reprogrammable Gate Array and Applications", S. Trimberger, Proceedings of the IEEE, July 1993 (not a document link)
[12] "Look, Ma-No Fabs!", J. Shelton, R. Pepper; IEEE Solid State Circuits Magazine, v3 n4 ,Nov. 7, 2011 (not a document link)
[13] Xilinx CTO Bill Carter Oral History (Computer History Museum) Includes descriptions of his close relationship with Xilinix co-founders Ross Freeman and Bernie Vonderschmitt
[14] Chips and Technologies Wikipedia page
[15] "Field-Programmable Gate Arrays", S.D. Brown, R.F. Francis, J. Rose, Z.G. Vranesic, Kluwer Academic Publishers, 1992
[16] Fabless Manufacturing Wikipedia page
[17] The Global Semiconductor Alliance (GSA)
[18] Remembering Ross Freeman EDN story by Loring Wirbel (Feb. 27, 2009)
[19] FPGA Market Size & Growth (May 2025)
[20] Benefits of FPGA in Healthcare
[21] FPGA Applications in Radio Astronomy
[22] FPGAs for Scientific HPC Applications
[23] FPGAs in Cryptography
Supporting materials (supported formats: GIF, JPEG, PNG, PDF, DOC): All supporting materials must be in English, or if not in English, accompanied by an English translation. You must supply the texts or excerpts themselves, not just the references. For documents that are copyright-encumbered, or which you do not have rights to post, email the documents themselves to ieee-history@ieee.org. Please see the Milestone Program Guidelines for more information.
Please email a jpeg or PDF a letter in English, or with English translation, from the site owner(s) giving permission to place IEEE milestone plaque on the property, and a letter (or forwarded email) from the appropriate Section Chair supporting the Milestone application to ieee-history@ieee.org with the subject line "Attention: Milestone Administrator." Note that there are multiple texts of the letter depending on whether an IEEE organizational unit other than the section will be paying for the plaque(s).
Please recommend reviewers by emailing their names and email addresses to ieee-history@ieee.org. Please include the docket number and brief title of your proposal in the subject line of all emails.
