Milestone-Proposal:Development of the Field Programmable Gate Array
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Docket #:2021-02
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To the proposer’s knowledge, is this achievement subject to litigation? No
Is the achievement you are proposing more than 25 years old? Yes
Is the achievement you are proposing within IEEE’s designated fields as defined by IEEE Bylaw I-104.11, namely: Engineering, Computer Sciences and Information Technology, Physical Sciences, Biological and Medical Sciences, Mathematics, Technical Communications, Education, Management, and Law and Policy. Yes
Did the achievement provide a meaningful benefit for humanity? Yes
Was it of at least regional importance? Yes
Has an IEEE Organizational Unit agreed to pay for the milestone plaque(s)? Yes
Has the IEEE Section(s) in which the plaque(s) will be located agreed to arrange the dedication ceremony? Yes
Has the IEEE Section in which the milestone is located agreed to take responsibility for the plaque after it is dedicated? Yes
Has the owner of the site agreed to have it designated as an IEEE Milestone? Yes
Year or range of years in which the achievement occurred:
Title of the proposed milestone:
Development of the Field Programmable Gate Array
Plaque citation summarizing the achievement and its significance; if personal name(s) are included, such name(s) must follow the achievement itself in the citation wording: Text absolutely limited by plaque dimensions to 70 words; 60 is preferable for aesthetic reasons.
In 1984, Ross Freeman co-founded Xilinx to productize his FPGA invention: an integrated circuit whose Boolean logic functions and interconnects were software-programmable and reprogrammable after manufacture. Introduced in 1985, the XC2064 incorporated 64 4-input logic functions. With Moore's Law scaling, FPGAs became a hugely successful electronic component for nearly any application, including high-performance digital signal processing (DSP), data routing in the internet infrastructure, mobile telephony, and high-performance computation.
200-250 word abstract describing the significance of the technical achievement being proposed, the person(s) involved, historical context, humanitarian and social impact, as well as any possible controversies the advocate might need to review.
In the early 1980s, custom integrated circuits, commonly called Application Specific ICs (ASICs), were available from many companies, and were supported by the nascent Electronic Design Automation (EDA) industry. Programmable Logic Devices (PLDs) were programmable, pre-manufactured devices with a simple fixed architecture, and were programmable with simple software. However, PLDs scaled poorly with process technology, both in area and performance.
The Field Programmable Gate Array (FPGA), with both programmable logic and interconnect, made significant advances over the PLD. The programmable interconnect enabled the FPGA to scale with process technology scaling (aka, Moore’s Law), albeit at the cost of ASIC-like placement and routing to fit a design into the FPGA. FPGA vendors were forced to write their own physical EDA software, competing not only against ASIC and PLD companies, but also against the EDA industry.
The innovation to program FPGAs by writing on-chip memory cells relieved the requirement that the devices use EEPROM or antifuse technology, at the cost of many more transistors. However, since FPGAs scaled with process technology, that cost faded over time. Significantly, FPGAs were able to leverage advanced process nodes early. Their process technology advantage mitigated their transistor count disadvantage.
FPGAs grew in complexity over the years, adding memory, arithmetic, high-speed I/O transceivers, cryptography, analog interfaces, and microprocessors to their logic components. As a result, FPGAs opened up access to advanced process technology to many more designers that ASIC companies could. This access permitted FPGAs to be deployed in advanced applications, including early internet routers and AI/ML hardware.
IEEE technical societies and technical councils within whose fields of interest the Milestone proposal resides.
IEEE Computer Society
In what IEEE section(s) does it reside?
Santa Clara Valley Section
IEEE Organizational Unit(s) which have agreed to sponsor the Milestone:
IEEE Organizational Unit(s) paying for milestone plaque(s):
Unit: Santa Clara Valley Section
Senior Officer Name: Taylor Winship
IEEE Organizational Unit(s) arranging the dedication ceremony:
Unit: Santa Clara Valley Section
Senior Officer Name: Taylor Winship
IEEE section(s) monitoring the plaque(s):
IEEE Section: Santa Clara Valley Section
IEEE Section Chair name: Taylor Winship
Milestone proposer(s):
Proposer name: Brian Berg
Proposer email: Proposer's email masked to public
Please note: your email address and contact information will be masked on the website for privacy reasons. Only IEEE History Center Staff will be able to view the email address.
Street address(es) and GPS coordinates in decimal form of the intended milestone plaque site(s):
Describe briefly the intended site(s) of the milestone plaque(s). The intended site(s) must have a direct connection with the achievement (e.g. where developed, invented, tested, demonstrated, installed, or operated, etc.). A museum where a device or example of the technology is displayed, or the university where the inventor studied, are not, in themselves, sufficient connection for a milestone plaque.
Please give the address(es) of the plaque site(s) (GPS coordinates if you have them). Also please give the details of the mounting, i.e. on the outside of the building, in the ground floor entrance hall, on a plinth on the grounds, etc. If visitors to the plaque site will need to go through security, or make an appointment, please give the contact information visitors will need.
Are the original buildings extant?
Details of the plaque mounting:
How is the site protected/secured, and in what ways is it accessible to the public?
Who is the present owner of the site(s)?
What is the historical significance of the work (its technological, scientific, or social importance)? If personal names are included in citation, include detailed support at the end of this section preceded by "Justification for Inclusion of Name(s)". (see section 6 of Milestone Guidelines)
FPGAs gave access to leading-edge semiconductor technology for vastly more designers than ASIC technology could provide. The ASIC design process was long and complex, requiring expertise from process technology to systems design, packaging, and test program development. ASIC vendors could not provide sufficient assistance for a large number of customers. As such, small customers were turned away.
FPGAs eliminated the costly mask tooling required for an ASIC design. This expense, borne up-front, months before the device could be used in a system, was prohibitive for many potential customers.
FPGAs eliminated the lengthy time-lag from completion of the design until the manufacturing cycle was complete. Many ASIC designs became obsolete during that manufacturing cycle. It was estimated that despite the up-front NRE and design investment, only about one-third of ASIC designs survived to go into production.
Because of their immediate availability and flexibility, FPGAs were the implementation of choice for emerging standards and computation. FPGAs accelerated development of a broad range of applications, including ASIC emulation, network routers, PCI and other interface standards, and AI/ML algorithms.
Even with modern EDA software, large semiconductor devices are difficult to design, requiring a broad range of skills from system design, logic design, circuit design, transistor-level modeling, test program generation, package design, and signal integrity. By providing a pre-manufactured device, FPGAs eliminated whole classes of problems for their users, facilitating the deployment of custom silicon in a broad range of applications.
Simultaneously with FPGA device definition and product development, FPGA companies pioneered the “fabless” semiconductor company, thereby eschewing construction of a semiconductor manufacturing facility and instead enlisting semiconductor manufacturers to become “foundries” to build the FPGA device. Both models - the “fabless” semiconductor company and the “foundry” - became common, and they were non-existent before the FPGA.
Justification for Inclusion of Name(s) Ross Freeman is cited as the inventor of the FPGA. He is acknowledged in the inventors Hall of Fame for this. His genius enabled him to see past the technological limitations of the day. At the time of the FPGA's invention, there were dozens of ASIC companies. Successful ASIC companies delivered the fastest, the lowest-cost, or the highest-capacity devices. Because of the enormous overhead of the field programmability, FPGAs were slow, expensive, and low-capacity. Ross Freeman understood process scaling would address these drawbacks, and proposed an architecture that could leverage scaling to deliver the device.
What obstacles (technical, political, geographic) needed to be overcome?
When FPGAs were introduced, the semiconductor technology was barely able to provide enough transistors to allow the creation of a simple FPGA. The initial obstacle was the definition of an architecture that was efficient enough to be built with the technology at the time, yet capable enough in capacity and performance to support useful functionality.
As efficient FPGA architecture was unlike ASIC cell-based or gate array architecture, commercial EDA was unsuitable. FPGA logic blocks were unlike the gates in gate arrays or cell-based designs, so commercial synthesis performed poorly. Commercial placement and routing similarly did not consider the uniqueness of FPGA programmable routing. As commercial EDA vendors were unwilling to modify their tools, FPGA vendors were required to implement their own tools for synthesis, placement, and routing.
A significant advantage that FPGA vendors gained from building their own tools was that they were able to innovate their architectures continually. They thereby improved the quality of the FPGAs, not only in improved logic and interconnect architecture, but also with the inclusion of additional functionality beyond simple logic: memory, arithmetic, analog interfaces, high-speed I/O, and even microprocessors.
What features set this work apart from similar achievements?
FPGAs included both programmable logic and interconnect. In stark contrast to PLDs, whose architecture limited them to hundreds of gates of equivalent logic, FPGA's programmable interconnect permitted them to scale with semiconductor process scaling to millions of gates.
Programmable interconnect enabled the inclusion of additional types of logic blocks, including memory, arithmetic, ADC, transceivers, microprocessors, and AI/ML fabric.
FPGAs programmed using SRAM-style memory cells were able to leverage the most advanced process nodes as soon as they were available. FPGAs replaced memories as process drivers for logic processes, accelerating the development of new nodes.
FPGAs provided a significant advantage over mask-programmed custom logic: first, by being immediately available as there was no need to wait through a lengthy fabrication cycle; and second, by eliminating whole classes of engineering required to deliver a product. These classes included detailed circuit design, test program development, and packaging design.
Why was the achievement successful and impactful?
Beyond the usual requirement of a huge amount of hard work, FPGAs were successful because:
• The novel architecture allowed FPGA capacity, performance and power to scale with process technology advances. Since the invention of the FPGA, device capacity has grown more than a million-fold, and FPGA capacity has grown similarly.
• Fundamental questions in device architecture for the logic block and its interconnect network were resolved in a way that were efficient in implementation, and delivered good specification numbers.
• FPGAs were not simply a semiconductor device. FPGA offerings included EDA software and intellectual property (IP) to enable users to use the device. The FPGA, with its EDA and IP, comprised a computation solution that was analogous to a computer made up of a microprocessor, compiler and libraries. This combination enabled deployment of FPGAs in high-performance communications and computation, leading to their inclusion in data centers for performing database operations and AI/ML.
• A major part of the FPGA value proposition was the low Non-Recurring Engineering (NRE) costs compared to the ASIC. These costs included manufacturing tooling and expensive EDA tools, and also included the months-long integrated circuit custom manufacturing cycle.
Supporting texts and citations to establish the dates, location, and importance of the achievement: Minimum of five (5), but as many as needed to support the milestone, such as patents, contemporary newspaper articles, journal articles, or chapters in scholarly books. 'Scholarly' is defined as peer-reviewed, with references, and published. You must supply the texts or excerpts themselves, not just the references. At least one of the references must be from a scholarly book or journal article. All supporting materials must be in English, or accompanied by an English translation.
Supporting materials (supported formats: GIF, JPEG, PNG, PDF, DOC): All supporting materials must be in English, or if not in English, accompanied by an English translation. You must supply the texts or excerpts themselves, not just the references. For documents that are copyright-encumbered, or which you do not have rights to post, email the documents themselves to ieee-history@ieee.org. Please see the Milestone Program Guidelines for more information.
Please email a jpeg or PDF a letter in English, or with English translation, from the site owner(s) giving permission to place IEEE milestone plaque on the property, and a letter (or forwarded email) from the appropriate Section Chair supporting the Milestone application to ieee-history@ieee.org with the subject line "Attention: Milestone Administrator." Note that there are multiple texts of the letter depending on whether an IEEE organizational unit other than the section will be paying for the plaque(s).
Please recommend reviewers by emailing their names and email addresses to ieee-history@ieee.org. Please include the docket number and brief title of your proposal in the subject line of all emails.
