Difference between revisions of "Milestone-Proposal:Whirlwind Computer"

(Article updated via HTTP request)
(Article updated via HTTP request)
Line 12: Line 12:
 
3. IEEE Global History Network "Magnetic-Core Memory".  
 
3. IEEE Global History Network "Magnetic-Core Memory".  
 
http://www.ieeeghn.org/wiki/index.php/Magnetic-Core_Memory
 
http://www.ieeeghn.org/wiki/index.php/Magnetic-Core_Memory
 
 
DESIGN AND CONSTRUCTION
 
DESIGN AND CONSTRUCTION
 
 
By 1947, Forrester and collaborator Robert Everett [http://www.cs.stthomas.edu/faculty/resmith/papers/WhirlwindR-127.pdf completed the design] of a high-speed stored-program computer for this task. Most computers of the era operated in "bit-serial" mode, using single-bit arithmetic and feeding in large words, often 48 or 60 bits in size, one bit at a time. This was simply not fast enough for their purposes, so Whirlwind included sixteen such math units, operating on a complete 16-bit word every cycle in "bit-parallel" mode. Ignoring memory speed, Whirlwind was essentially sixteen times as fast as other machines. Today almost all CPUs do arithmetic in "bit-parallel"; some CPUs extend the idea to larger 32- or 64-bit words.
 
By 1947, Forrester and collaborator Robert Everett [http://www.cs.stthomas.edu/faculty/resmith/papers/WhirlwindR-127.pdf completed the design] of a high-speed stored-program computer for this task. Most computers of the era operated in "bit-serial" mode, using single-bit arithmetic and feeding in large words, often 48 or 60 bits in size, one bit at a time. This was simply not fast enough for their purposes, so Whirlwind included sixteen such math units, operating on a complete 16-bit word every cycle in "bit-parallel" mode. Ignoring memory speed, Whirlwind was essentially sixteen times as fast as other machines. Today almost all CPUs do arithmetic in "bit-parallel"; some CPUs extend the idea to larger 32- or 64-bit words.
  
The word size was selected after some deliberation. The machine worked by passing in a single address with almost every instruction, thereby reducingFact|date=April 2008 the number of memory accesses. For operations with two operands, adding for instance, the "other" operand was assumed to be the last one loaded. Whirlwind operated much like a reverse Polish notation calculator in this respect; except there was no operand stack, only an accumulator. The designers felt that 2000 words of memory would be the minimum usable amount, requiring 11 bits to represent an address, and that 16 to 32 instructions would be the minimum for another 5 bits -- and so it was 16-bits. Nevertheless the small word size led John von Neumann to conclude the machine would be worthless.
+
The word size was selected after some deliberation. The machine worked by passing in a single address with almost every instruction, thereby reducingFact|a5=TECHNICAL DESCRIPTION
 
 
The Whirlwind design incorporated a control store driven by a master clock. Each step of the clock selected a signal line in a diode matrix that enabled gates and other circuits on the machine. A special switch directed signals to different parts of the matrix to implement different instructions. The design inspired Maurice Wilkes to develop the concept of microprogramming.
 
 
 
Construction of the machine started the next year, an effort that employed 175 people including 70 engineers and technicians. Whirlwind took 3 years to build and first went online on April 20, 1951. The project's budget was $1 million a year, and after three years the Navy had already lost interest. The USAF picked up the work under "Project Claude".
 
 
 
The core of the machine
 
 
 
Speed of the original design (20 KIPS) turned out to be too slow to be very useful, and most of the problem was attributed to the fairly slow speed of the Williams tubes (or, more accurately, Williams-Kilburn tubes) used for main memory of 256 words. Forrester started looking at replacements, first using magnetic tape formed into spirals, even at one time considering using a 3-D array of neon lamps, and eventually creating core memory. Speed was roughly doubled (40 KIPS) as a result of using core when the new version was completed in 1953. The addition time was 49 microseconds and the multiplication time was 61 microseconds (before the main memory was converted to magnetic core).
 
 
 
After the magnetic core memory was installed, the Whirlwind became the fastest computer of its time. With the change it had an addition time of 8 microseconds, a multiplication time of 25.5 microseconds, and a division time of 57 microseconds (excluding memory access time). The access time had been about 16 microseconds for the CRT memory which was reduced to only 8 microseconds with the magnetic core.
 
 
 
 
 
 
 
FURTHER READING
 
Redmond, Kent, and Thomas Smith. Project Whirlwind: The History of a Pioneer Computer. Bedford, MA: Digital Press, 1980.
 
Everett, Robert R. A History of Computing in the Twentieth Century, chapter on Whirlwind. Academic Press, 1980.
 
 
 
Wildes, Karl, and Nilo Lindgren. A Century of Electrical Engineering and Computer Science at MIT, 1882-1982, chapter 17 "From Whirlwind to SAGE,” 280-301. Cambridge: MIT Press, 1985, pages 280-301.|a5=TECHNICAL DESCRIPTION
 
 
By 1947, Forrester and collaborator Robert Everett completed the design of a high-speed stored-program computer.  Most computers of the era operated in "bit-serial" mode, using single-bit arithmetic and feeding in large words, often 48 or 60 bits in size, one bit at a time. This was simply not fast enough for their purposes, so Whirlwind included sixteen such math units, operating on a complete 16-bit word every cycle in "bit-parallel" mode. Ignoring memory speed, Whirlwind was essentially sixteen times as fast as other machines. Today almost all CPUs do arithmetic in "bit-parallel"; some CPUs extend the idea to larger 32- or 64-bit words.
 
By 1947, Forrester and collaborator Robert Everett completed the design of a high-speed stored-program computer.  Most computers of the era operated in "bit-serial" mode, using single-bit arithmetic and feeding in large words, often 48 or 60 bits in size, one bit at a time. This was simply not fast enough for their purposes, so Whirlwind included sixteen such math units, operating on a complete 16-bit word every cycle in "bit-parallel" mode. Ignoring memory speed, Whirlwind was essentially sixteen times as fast as other machines. Today almost all CPUs do arithmetic in "bit-parallel"; some CPUs extend the idea to larger 32- or 64-bit words.
  
The word size was selected after some deliberation. The machine worked by passing in a single address with almost every instruction, thereby reducingFact|a6=|a7=|a8=No|a9=|a10=|a11=No|a12=|a13name=|a13section=|a13position=|a13email=|a14name=|a14ou=|a14position=|a14email=|a15Aname=|a15Aemail=|a15Aname2=|a15Aemail2=|a15Bname=|a15Bemail=|a15Bname2=|a15Bemail2=|a15Cname=|a15Ctitle=|a15Corg=|a15Caddress=|a15Cphone=|a15Cemail=}}
+
The word size was selected after some deliberation. The machine worked by passing in a single address with almost every instruction, thereby reducingFact|a6=|a7=|a8=Yes|a9=The building where Whirlwind  was housed is  located at 211 Massachusetts Avenue, Cambridge. The plaque would be readily visible to pedestrians walking on the public sidewalk along this major street in Cambridge.|a10=MIT|a11=Yes|a12=Boston Section with support by one or more  Society Chapters.|a13name=Bruce Hecht|a13section=Boston|a13position=2010 Chair|a13email=Bruce.Hecht@analog.com|a14name=Robert Alongi|a14ou=Boston Section|a14position=Section Business Manager|a14email=sec.boston@ieee.org|a15Aname=Gilmore Cooke|a15Aemail=gilcooke@ieee.org|a15Aname2=|a15Aemail2=|a15Bname=c/o Robert Alongi|a15Bemail=sec.boston@ieee.org|a15Bname2=|a15Bemail2=|a15Cname=Gilmore Cooke|a15Ctitle=PE retired|a15Corg=Boston Section Committee|a15Caddress=8 Canvasback, W Yarmouth MA 02673|a15Cphone=617-759-4271|a15Cemail=gilcooke@ieee.org}}

Revision as of 17:30, 6 December 2010