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<div>{{Proposal<br />
|docketid=2021-12<br />
|litigation=No<br />
|more than 25 years=Yes<br />
|within fields of interest=Yes<br />
|benefit to humanity=Yes<br />
|regional importance=Yes<br />
|ou is paying=Yes<br />
|ou is arranging dedication=Yes<br />
|section is taking responsibility for plaque=Yes<br />
|a11=Yes<br />
|a3=1979 -1991<br />
|a1=Theoretical Foundation of Finite-Element-Method for Electromagnetics, 1979-1991<br />
|plaque citation=From 1979 to 1991, an electromagnetic-wave research group in the department of electrical <br />
engineering, National Taiwan University, laid the theoretical foundation for the Finite Element <br />
Method for general linear Electromagnetic field problems. They also found a straightforward<br />
derivation as a generalized Galerkin's method. It has been widely applied in academic <br />
researches and commercial software development, like the early versions of HFSS.<br />
<br />
1979 至 1991 期間，台大電機系的電波研究團隊建構了應用於一般線性電磁學問題的有限元素<br />
法理論基礎。他們也發現有限元素法的矩陣方程式，可以由推廣的 Galerkin 方法直接完成。這種<br />
推廣的 Galerkin 方法很快就應用到許多學術研究以及廣為應用的商業模擬軟體開發，如 HFSS。<br />
|a2b=IEEE Taipei Section<br />
|IEEE units paying={{IEEE Organizational Unit Paying<br />
|Unit=IEEE Taipei Section<br />
|Senior officer name=Kea-Tiong Tang, Chairman<br />
}}<br />
|IEEE units arranging={{IEEE Organizational Unit Arranging<br />
|Unit=IEEE Taipei Section<br />
|Senior officer name=Kea-Tiong Tang, Chairman<br />
}}<br />
|IEEE sections monitoring={{IEEE Section Monitoring<br />
|Section=IEEE Taipei Section<br />
|Section chair name=Kea-Tiong Tang, Chairman<br />
}}<br />
|Milestone proposers={{Milestone proposer<br />
|Proposer name=Shyh-Kang Jeng, Ruey-Beei Wu, and Jin-Fa Lee<br />
|Proposer email=skjeng@ntu.edu.tw, rbwu@ntu.edu.tw, and jin.fa.lee.1863@gmail.com<br />
}}<br />
|a2a=Department of Electrical Engineering, National Taiwan University, 1, Sec. 4, Roosevelt Rd., Taipei, Taiwan 10617. GPS coordinates: x 25.01953, y 121.54410<br />
|a7=The intended site is inside the main department building, which started its construction when Professor Chun Hsiung Chen, the team leader for the proposed milestone, served as the department head from 1982 to 1985. In this building, Professor Chen and his students in the team taught and developed further applications of the milestone. However, the major works of the proposed milestone were conducted earlier in the now civil engineering building, about 600 meters away. This building now accommodates more than 2500 students, including 800 undergraduates, 1200 master, and 500 Ph.D. students, reside to study various areas in electrical engineering. It is the "powerhouse" in Taiwan to promote the innovation, education, and promotion of electrical engineering for humanity.<br />
|a8=The original buildings where the development took place now serve a different goal, are no longer publicly accessible, and will probably be demolished within a few years.<br />
|mounting details=[[image:Varational electromagnetics plaque.jpg|thumb]] The intended location is near the entrance of the auditorium in the building, where the seminars, conferences, and invited lectures are frequently held. A picture giving an overview of the entrance of the auditorium is shown below. The IEEE can consult the department of Electrical Engineering about the exact place and mounting within the building<br />
|a9=The building is opened on weekdays. The site is protected/secured by a management team and security cameras.<br />
|a10=Chairman Chung-Chih Wu, Department of Electrical Engineering, National Taiwan University<br />
|a4=The Finite-Element Method (FEM) has been popular in modeling linear electromagnetic fields, <br />
from radiation, scattering, waveguide, to high-frequency circuits. To get a matrix equation for <br />
FEM, we have to derive a variational equation first. The applications of finite element methods <br />
for static fields were understood, and the variational nature of the formulation was well <br />
documented. However, for electromagnetic wave radiations and scattering problems, the <br />
underlying physics is non-Hermitian, and the corresponding variational principle was lacking in <br />
the 1980s. <br />
<br />
Consequently, the work's significance is: proposing a systematic method for derivation of <br />
variational equations, including exterior fields in the variational equations, and discovering a <br />
shortcut for deriving the FEM matrix equations directly. The inclusion of exterior field results in <br />
the popularity of the hybrid element method, and the shortcut method was a generalized <br />
Galerkin's method. Such a shortcut and the hybrid finite element method have been widely <br />
used for academic research and successful commercial software development, like the early <br />
versions of HFSS software (High-Frequency Structure Simulation).<br />
|a6=The major obstacles needed to be overcome by the FEM team led by Professor Chun Hsiung <br />
Chen (FEM@NTU) are: difficulty in treating non-self-adjoint fields, unsystematic methods for <br />
the variational formulation, difficulty in dealing with exterior fields, difficulty to find physical <br />
interpretation, tedious approaches for obtaining the FEM matrix equations, and challenge to <br />
prove that the proposed shortcut method is consistent with the proposed fundamental<br />
variational equation.<br />
<br />
'''Difficulty in Treating Non-self-adjoint fields'''<br />
<br />
Before 1980, most papers about variational formulation assume that the problem as an operator <br />
equation together with boundary conditions is self-adjoint. The inner product of a field with an <br />
operator operated on another field with associated boundary conditions is the same if we switch <br />
positions of the field and the operator. This reciprocity does not hold for a non-self-adjoint <br />
problem. For an example of the non-self-adjoint problem, consider the situation with <br />
anisotropic materials whose characteristics are described by non-symmetric and/or non-Hermitian matrices. <br />
<br />
The FEM@NTU team in 1980 first proposed a general variational formulation with an adjoint <br />
problem to handle a non-self-adjoint problem. The solution of the adjoint problem is related <br />
to problems with the material characteristics being the transpose or Hermitian of those of the <br />
original problem. Although the adjoint field is introduced, we still need to solve only the field <br />
distribution of the original problem with the FEM. The 1980 paper also provided physical <br />
interpretation through a concept of generalized reaction. However, it did not reveal how to <br />
extend the formulation for general exterior problems.<br />
<br />
'''Unsystematic derivation of variational formulation'''<br />
<br />
For mechanics, a variational equation is often obtained from the least action principle. For <br />
electromagnetics, the application of the FEM for exterior field problems is scarce before 1984.<br />
The most related papers are: Silvester and Hsieh (1971) [1], McDonald and Wexler (1972) [2], <br />
the Unimoment method (Mei, 1974) [3], and Morishita and Kumagai (1977) [4]. The variational <br />
equations in these works are derived case by case after setting up systems of partial differential <br />
equations from the Maxwell equation, except for Morishita and Kumagai in 1977, in which the <br />
formulation started from the least action principle generalized for electromagnetic fields. <br />
However, their approach is inconvenient and indirect for use since the formulation involves <br />
vector and scalar potentials.<br />
The FEM@NTU team first proposed in 1980 (primarily for interior problems and simple one-dimensional problems) [5] and 1984 (with extension to general exterior problems) [6] that the <br />
FEM equations for any linear Electromagnetic field problems can be deduced from setting the <br />
Fundamental Variational Principle (FVP) to be stationary, equivalent to the Maxwell equations<br />
along with the associated boundary conditions. Variational equations can be deduced simply <br />
by applying problem-dependent constraints to reduce the FVP. <br />
<br />
'''Difficulty in Dealing with Exterior Fields'''<br />
<br />
Silvester and Hsieh [1] applied Green's theorem to obtain a variational equation by treating the <br />
outer region as a single exterior element. However, they dealt with only 2D Laplace equations, <br />
i.e., static fields only. McDonald and Wexler [2] treated an Integral equation as a constraint to <br />
replace the exterior element. Their paper also shows that they can handle only 2-D Poisson <br />
equations, again, static fields only. Mei [3] proposed the unimoment method. He imposed an <br />
artificial boundary and expressed the exterior and interior fields as sums of eigenmodes and <br />
pseudo modes, respectively. A pseudo mode for the internal problem was obtained by the FEM <br />
with enforcing boundary conditions on the artificial boundary like an exterior eigenmode. The coefficients of both series were then acquired by matching the continuity conditions on the <br />
artificial boundary. The exterior field was not included in the variational equations directly.<br />
<br />
The FEM@NTU team expressed the exterior field in the following ways: a sum of eigenmodes <br />
(including scattering wave modes [6] and propagation modes in general waveguide [7]) or an <br />
integral over the artificial interior-exterior boundary [8]. Such expressions are then included<br />
in the functional with careful treatment for keeping their stationarity. In addition, the <br />
FEM@NTU team also proposed an attractive approach for dielectric waveguide problems. For <br />
such problems, 2-D transverse trial fields extending to infinity in the stationary functional are <br />
transformed into the inside of a closed region in the complex plane by a conformal mapping<br />
[9]. The exterior fields are thus taken into considerations automatically.<br />
<br />
'''Difficulty to Find Physical interpretation'''<br />
<br />
Many early publications about variational formulation describe their results with mathematic <br />
manipulation only. The variational principles derived by the FEM@NTU team in 1980 [5] and <br />
1984 [6] were with a physical interpretation of general reaction. Note also the stationarity of <br />
the FVP is equivalent to the Maxwell equations along with the boundary conditions, just like <br />
that the principle of virtual work is equivalent to Newton's laws in statics and dynamics. Also,<br />
in the 1984 paper [6], the FVP can be reduced to a form as oscillatory power if the problem is <br />
self-adjoint, which is similar to the least action principle for mechanics.<br />
<br />
'''Tedious Approaches for Obtaining the FEM matrix equations'''<br />
<br />
The process of obtaining a FEM matrix equation from the FVP by applying problem-related <br />
constraints and the Ritz procedure are pretty tedious, though systematic. The FEM@NTU <br />
team's 1985 paper introduced the Variational Reaction Theory (VRT) [10] to derive the required <br />
matrix equation and found it a generalization of the conventional Galerkin's method. <br />
<br />
'''Difficulty in Proving the Shortcut Being Consistent with the Fundamental Variational Equation'''<br />
<br />
The stationarity of the FVP proposed in 1984 [6] is equivalent to the Maxwell equations and <br />
should hold for all linear electromagnetic field problems. The VRT [10] is more efficient in <br />
deriving the required FEM matrix equations. However, its consistency with the variational <br />
equation of FVP was not clear. In other words, why does the generalized Galerkin's method <br />
work? Why does the way to deal with the exterior field in the generalized Galerkin's method <br />
lead to the correct solution? Such essential theoretical questions were answered in a FEM@NTU <br />
paper in 1988, in which the team proposed the concept of the Partial Variational Principle (PVP) <br />
[11]. By PVP, the variation on a functional of trial field f and its adjoint f<sup>a</sup>, like the partial <br />
differentiation, equals the sum of two functionals (PVPs), where one is obtained by taking partial <br />
variation with respect to f while the other is taken with respect to f<sup>a</sup>. If only field f is to be solved, <br />
the functional by taking partial variation to f can be ignored. The resultant partial variational <br />
principle is just the same as the starting equation of VRT. The consistency of VRT and the <br />
variational equation on the FVP is thus proved.<br />
|a5=Features of this series of work are given below:<br />
#First variational formulation equivalent to the Maxwell equations and associated boundary conditions. Also proposed are their physical interpretations.<br />
#A systematic approach to derive the FEM matrix equations.<br />
#First inclusion of exterior field in the variational equation, which leads to the now popular hybrid finite element method.<br />
#First shortcut to derive the FEM matrix equations directly, which is equivalent to a generalized Galerkin's method and widely used in academic and commercial software development circles.<br />
#A conformal mapping technique for dielectric waveguide problems to transform the two-dimensional transverse field into the inside of a closed region. Solving the fields in this closed region by the FEM handles the exterior fields automatically.<br />
<br />
'''Later development'''<br />
<br />
Since the FEM@NTU team published their 1985 papers, the generalized Galerkin's method <br />
becomes very popular in solving the scattering of objects in free space and waveguide <br />
structures. The primarily related papers are those introducing the transfinite element method <br />
(Lee and Cendes, 1987, 1987 [12], [13]; Cendes and Lee, 1988 [14]; Lee, Sun, and Cendes, 1991<br />
[15]), and those emphasizing hybrid finite element methods for the scattering of objects in free <br />
space (Jin and Liepa, 1988 [16]; Jin and Liepa, 1988 [17]). The transfinite element method was <br />
then applied for developing the commercial software HFSS for dealing with RF, microwave, and <br />
millimeter-wave circuits. The hybrid finite element method has also been proved efficient and <br />
effective in solving realistic scattering problems (for example, Jin and Volakis, 1991 [18] and <br />
Shen et al., 1998 [19]). However, the impact of the generalized Galerkin's method is not limited <br />
by its applications to solving electromagnetic wave problems with the finite element methods. <br />
Professor Jin-Fa Lee at the Ohio State University also recognized the strong correlation of the <br />
generalized Galerkin's method with the reciprocity theorem in electromagnetic fields and the <br />
popular Bi-CG methods for solving complex symmetric but non-Hermitian matrices equations.<br />
<br />
'''The FEM@NTU team'''<br />
<br />
The FEM@NTU leader, Professor Chen, is the first faculty in Taiwan who published papers in <br />
IEEE journals (as early as 1970 [20]). He and his students published their first FEM paper on <br />
applying the FEM to a one-dimensional problem with inhomogeneous dielectric in free space <br />
in 1979 [21], [22] and a rectangular waveguide in 1981 [23]. Later the FEM@NTU team began <br />
to focus on finding a general variational equation for electromagnetic field problems. They <br />
published papers on the fundamental variational principles (FVP) in 1980 [5] and 1984 [6], <br />
respectively. A shortcut, the VRT, for deriving FEM matrix equations from the FVP was then <br />
proposed in their 1985 paper [10]. Finally, in 1988, the FEM@NTU team proposed the partial <br />
variational principle [11] and proved that the VRT is consistent with the variational equation on <br />
the FVP.<br />
<br />
Not restricted to pure and abstract mathematic formulation, based on the FVP, VRT, and PVP, <br />
Professor Chen and his students published various applications. The applications include: the <br />
scattering of the perfect electric conductor (PEC) cylinder with inhomogeneous dielectric <br />
coating [6], general scattering from anisotropic inhomogeneous slabs [24], [25] and cylinders<br />
[26], scattering from a magnetostatic slab in parallel-plate waveguide [7], general analysis of <br />
dielectric waveguides [8], [10], birefringence analysis of anisotropic optical fibers [27], and <br />
analysis of discontinuities in a dielectric waveguide [11] and planar dielectric waveguides [28], <br />
and planar dielectric antennas [29], For weakly guiding dielectric waveguides [9], microstrip lines<br />
[30], [31], and coplanar waveguides [32], [33], the FEM@NTU team conceived a delicate idea, <br />
the Variational Conformal Mapping technique [9], to transform the problem onto a complex <br />
plane, and wherein solve a scalar field.<br />
<br />
'''Further information'''<br />
<br />
Jin-Fa Lee is the major developer of the booming commercial software HFSS. He took <br />
Professor Chen's course on mathematical physics, which introduced variational formulation <br />
coupled with the FEM in 1981 when he was an undergraduate student in the National Taiwan <br />
University's electric engineering department. Afterward, he pursued his Ph.D. studies at<br />
Carnegie Mellon University under the supervision of Professor Zoltan J. Cendes, father of HFSS <br />
and the founder of Ansoft Corp. Note Ansoft Corp. was later acquired by Ansys Corp.<br />
|references='''1. General variational principle for interior field problems and simple one-dimensional <br />
transmission-reflection problems'''<br />
<br />
The work [5] is included as a reference in Chapter 6, Variational Principles for Electromagnetics, <br />
The Finite Element Method in Electromagnetics, by Jianming Jin, New York, USA: John Wiley & <br />
Sons, Inc., 1993, a popular textbook for learning the FEM for electromagnetics. In that chapter, <br />
Professor Jin commented on the use of variational equations as: "It is only in recent years that <br />
the variational formulation has been discussed more extensively, mainly to satisfy the need for <br />
finite element method … However, even these methods remain unknown to many researchers <br />
and generally are not taught to graduate students. This situation is in contrast to that of <br />
Galerkin's method, which is a popular choice both in research and instruction, possibly because <br />
of its simplicity."<br />
<br />
We agree that starting the FEM with a general variational formulation requires much<br />
mathematical background, and its derivation is not as straightforward as the generalized <br />
Galerkin's method. However, the FEM@NTU team also found this shortcut [10] and provided <br />
it with a more rigorous theoretical foundation [11].<br />
<br />
Jin also said: "If we indeed establish a general procedure to derive the variational formulation <br />
for any given problem, there will be no major obstacles, except for personal preference, to <br />
prevent us from employing the variational method for the finite element formulation." Here Jin <br />
skipped our general variational equation of FVP, which could be due to the abstract <br />
mathematics in the FEM@NTU work [6], especially in including the exterior field into the <br />
variational equation. Actually, in Jin's book, the functional given is derived from the <br />
generalized Galerkin's method while fine-tuning some boundary terms to ensure that the <br />
functional is stationary.<br />
<br />
Another book, Finite Elements for Wave Electromagnetics: Method and Techniques edited by <br />
Peter P. Silvester and Giuseppe Pelosi, New York, USA: IEEE Press, 1994, collected papers <br />
important to applications of the FEM to electromagnetics. The FEM@NTU contributions [5]<br />
about the general variational formulation and [25] about the VRT were included.<br />
<br />
'''2. Fundamental Variational Principle (FVP) and inclusion of exterior field as hybrid finite <br />
element method'''<br />
<br />
The FVP was proposed in 1984 [6]. It has been applied to model the scattering matrix <br />
coefficients for microwave circuit elements, such as [7]. The transfinite element method in [14] <br />
used a similar approach, though the FEM matrix equations are obtained from the generalized <br />
Galerkin's method. <br />
<br />
A similar approach with another hybrid finite element method for dielectric waveguide analysis<br />
was utilized by Su [8], also Professor Chun Hsiung Chen's student.<br />
<br />
Such a hybrid finite element method for scattering problems was a contribution of Jin [16].<br />
<br />
'''3. Variational Reaction Theory (VRT) as a generalized Glerkin's method'''<br />
<br />
As mentioned above, the VRT [10] became a popular shortcut as a generalized Galerkin's <br />
method in deriving equations for FEM. A lot of published FEM works were based on this <br />
approach. One typical example is applying the VRT to arbitrary two-dimensional <br />
electromagnetic problems with general anisotropic material [26]. Based on a unified (E_z, H_z)<br />
formulation, the scattering problem when a plane wave is obliquely incident upon an <br />
inhomogeneous and anisotropic dielectric cylinder. The variational equation is then derived <br />
with all the exterior problem absorbed into the boundary operator and then solved by the finite <br />
element method. The scattering cross sections of radiation problems can be obtained. In <br />
addition, the guiding problems of dielectric waveguides are also solved by considering <br />
obliquely incident inhomogeneous waves.<br />
<br />
'''4. Partial Variational Principle to connect the VRT and the FVP and its applications to the <br />
analysis of discontinuities in dielectric waveguides'''<br />
<br />
This is the topic of the FEM@NTU paper in 1988 [11]. Its two further similar applications are <br />
published in 1989 [28] and 1990 [29]. <br />
<br />
'''5. Variational Conformal Mapping Techniques'''<br />
<br />
The 1986 paper of the FEM@NTU proposed such an idea in [9] for dielectric waveguide <br />
problems. Because it applied a clever idea to map the scalar potentials in the transverse plane <br />
into the complex plane. The original exterior field distribution is now in a closed region and can <br />
be solved easily by the FEM. With such a technique, problems with edge singularities like the <br />
microstrip and coplanar waveguide propagation problems can also be taken care of easily. <br />
References [30]-[33] are good examples.<br />
<br />
[1] P. Silvester and M.-S. Hsieh, "Finite-element solution of 2-dimensional exterior-field <br />
problems," Proceedings of the Institution of Electrical Engineers, vol. 118, no. 12, pp. <br />
1743 – 1747, 1971. doi: 10.1049/piee.1971.0320<br />
<br />
[2] B. H. McDonald and A. Wexler, "Finite-element solution of unbounded field problems," <br />
IEEE Transactions on Microwave Theory and Techniques, vol. 20, no. 12, pp. 841-<br />
847, Dec. 1972. doi: 10.1109/TMTT.1972.1127895.<br />
<br />
[3] K. Mei, "Unimoment method of solving antenna and scattering problems," IEEE <br />
Transactions on Antennas and Propagation, vol. 22, no. 6, pp. 760-766, Nov. 1974. <br />
doi: 10.1109/TAP.1974.1140894.<br />
<br />
[4] K. Morishita and N. Kumagai, "Unified approach to the derivation of variational <br />
expression for electromagnetic fields," IEEE Transactions on Microwave Theory and <br />
Techniques, vol. 25, no. 1, pp. 34-40, Jan. 1977. doi: 10.1109/TMTT.1977.1129027.<br />
<br />
[5] C. H. Chen and C.-D. Lien, "The variational principle for non-self-adjoint<br />
electromagnetic problems," IEEE Transactions on Microwave Theory and Techniques, <br />
vol. MTT-28, no. 8, pp. 878-886, Aug. 1980. doi: 10.1109/TMTT.1980.1130186.<br />
<br />
[6] S.-K. Jeng and C. H. Chen, "On variational electromagnetics: Theory and application,"<br />
IEEE Transactions on Antennas and Propagation, vol. AP-32, no. 9, pp. 902-907, Sept.<br />
1984. doi: 10.1109/TAP.1984.1143439<br />
<br />
[7] H.-C. Chang, S.-K. Jeng, R.-B. Wu, and C. H. Chen," Propagation of waves through <br />
magnetoplasma slab within a parallel-plate guide," IEEE Transactions on Microwave <br />
Theory and Techniques, vol. MTT-34, no. 1, pp. 50-54. Jan. 1986, doi: 10.1109/8.1074<br />
<br />
[8] C.-C. Su, "A combined method for dielectric waveguides using the finite-element <br />
technique and surface integral equations method," IEEE Transactions on Microwave <br />
Theory and Techniques, vol. MTT-34, no. 11, pp. 1140-1146, Nov. 1986. doi: 10.1109/<br />
TMTT.1986.1133511<br />
<br />
[9] R.-B. Wu and C. H. Chen, "A scalar variational conformal mapping technique for weakly <br />
guiding dielectric waveguides," IEEE Journal of Quantum Electronics, vol. QE-22, no. <br />
3, 1986, pp. 603-609. doi: 10.1109/JQE.1986.1073014<br />
<br />
[10] R.-B. Wu and C. H. Chen, "On the variational reaction theory for dielectric <br />
waveguides," IEEE Transactions on Microwave Theory and Techniques, vol. MTT-33, <br />
no. 6, pp. 477-483, June 1985. doi: 10.1109/TMTT.1985.1133102<br />
<br />
[11] S.-J. Chung and C. H. Chen, "Partial variational principle for electromagnetic field <br />
problems: Theory and applications," IEEE Transactions on Microwave Theory and <br />
Techniques, vol. MTT-36, no. 3, pp. 473-479, Mar. 1988. doi: 10.1109/22.3537<br />
<br />
[12] J.‐F. Lee and Z. J. Cendes, "Transfinite elements: A highly efficient procedure for <br />
modeling open field problems," Journal of Applied Physics 61, 3913 (1987). https:// <br />
doi.org/10.1063/1.338582<br />
The variational formulation in this paper is similar to the one in a FEM@NTU 1982 <br />
paper: S.-K. Jeng and C. H. Chen, "A new variational theory for linear field problems <br />
and its application to electrostatics," Journal of the Chinese Institute of Engineers, vol. <br />
5, no. 2, 1982, pp. 99-107. https://doi.org/10.1080/02533839.1982.9676696<br />
<br />
[13] J.-F. Lee and Z. J. Cendes, "The transfinite element method for computing <br />
electromagnetic scattering from arbitrary lossy cylinders," in 1987 International <br />
Symposium on Antennas and Propagation, pp. 99-102, Jan. 1987, doi: 10.1109/<br />
APS.1987.1150085.<br />
The variational formulation in this paper is similar to the one derived in a FEM@NTU <br />
1984 paper [6].<br />
<br />
[14] Z. J. Cendes and J.-F. Lee, "The transfinite element method for modeling MMIC <br />
devices," IEEE Transactions on Microwave Theory and Techniques, vol. 36, no. 12, <br />
pp. 1639-1649, Dec. 1988. doi: 10.1109/22.17395.<br />
,<br />
<br />
[15] J. F. Lee, D. K. Sun and Z. J. Cendes, "Tangential vector finite elements for <br />
electromagnetic field computation," IEEE Transactions on Magnetics, vol. 27, no. 5, <br />
pp. 4032-4035, Sept. 1991. doi: 10.1109/20.104986.<br />
<br />
[16] J.-M. Jin and V. V. Liepa, "Application of hybrid finite element method to <br />
electromagnetic scattering from coated cylinders," IEEE Transactions on Antennas <br />
and Propagation, vol. 36, no. 1, Jan. 1988, pp. 50-54. doi: 10.1109/8.1074<br />
<br />
[17] J.-M. Jin and V. V. Liepa, "A note on hybrid finite element method for solving scattering <br />
problems," IEEE Transactions on Antennas and Propagation, vol. 36, no. 10, pp. 1486-<br />
1490, Oct. 1988. doi: 10.1109/8.8638.<br />
<br />
[18] J.-M. Jin and J. L. Volakis, "Scattering and radiation from microstrip patch antennas <br />
and arrays residing in a cavity," in 1991 International Symposium on Antennas and <br />
Propagation, pp. 657-660 vol.2. 1991, doi: 10.1109/APS.1991.174925.<br />
<br />
[19] X.-Q. Sheng, J.-M. Jin, J. Song, C.-C. Lu, and W. C. Chew, "On the formulation of <br />
hybrid finite-element and boundary-integral methods for 3-D scattering," IEEE <br />
Transactions on Antennas and Propagation, vol. 46, no. 3, pp. 303-311, March 1998.<br />
doi: 10.1109/8.662648.<br />
<br />
[20] C. H. Chen, "Some remarks on exterior electromagnetic boundary value problems for <br />
spheres," IEEE Transactions on Antennas and Propagation, vol. 18, no. 5, pp. 705-<br />
707, Sept. 1970. doi: 10.1109/TAP.1970.1139747.<br />
<br />
[21] C. H. Chen and C.-D. Lien, "A finite element solution of the wave propagation problem <br />
for an inhomogeneous dielectric slab," IEEE Transactions on Antennas and <br />
Propagation, vol. 27, no. 6, pp. 877-880, Nov. 1979. doi: 10.1109/TAP.1979.1142199.<br />
<br />
[22] C.-H. Chen and Y.-W. Kiang, "A variational theory for wave propagation in a one-dimensional inhomogeneous medium," IEEE Transactions on Antennas and <br />
Propagation, vol. 28, no. 6, pp. 762-769, Nov. 1980. doi: 10.1109/TAP.1980.1142435.<br />
<br />
[23] C.-T. Liu and C. H. Chen, "A variational theory for wave propagation in inhomogeneous <br />
dielectric slab loaded waveguides," IEEE Transactions on Microwave Theory and <br />
Techniques, vol. 29, no. 8, pp. 805-812, Aug. 1981. doi: 10.1109/TMTT.1981.1130451.<br />
<br />
[24] S.-K. Jeng and C. H. Chen, "Variational finite element solution of electromagnetic wave <br />
propagation in a one‐dimensional inhomogeneous anisotropic medium," Journal of <br />
Applied Physics 55, 630, 1984. https://doi.org/10.1063/1.333115<br />
<br />
[25] S.-K. Jeng, R.-B. Wu and C. H. Chen, "Waves obliquely incident upon a stratified <br />
anisotropic slab: A variational reaction approach," Radio Science, vol. 21, no. 4, pp. <br />
681-688, July-Aug. 1986, doi: 10.1029/RS021i004p00681.<br />
<br />
[26] R.-B. Wu and C. H. Chen, "Variational reaction formulation of scattering problem for <br />
anisotropic dielectric cylinders," IEEE Transactions on Antennas and Propagation, vol. <br />
34, no. 5, pp. 640-645, May 1986, doi: 10.1109/TAP.1986.1143874.<br />
<br />
[27] R.-B. Wu and C. H. Chen, "Birefringence analysis of anisotropic optical fibers using <br />
variational reaction theory," IEEE Transactions on Microwave Theory and Techniques, <br />
vol. 34, no. 6, pp. 741-745, June 1986, doi: 10.1109/TMTT.1986.1133428.<br />
<br />
[28] S.-J. Chung and C. H. Chen, "A partial variational approach for arbitrary discontinuities <br />
in planar dielectric waveguides," IEEE Transactions on Microwave Theory and <br />
Techniques, vol. MTT-37, no. 1, pp. 208 - 214, Jan. 1989. doi: 10.1109/22.20040<br />
<br />
[29] S.-J. Chung and C. H. Chen, "A partial variational analysis of planar dielectric <br />
antennas," IEEE Transactions on Antennas and Propagation, vol. 39, no. 6, pp. 713 -<br />
718, Jun. 1991. doi: 10.1109/8.86867<br />
<br />
[30] C. Shih, R. -B. Wu, S.-K. Jeng, and C. H. Chen, "A full-wave analysis of microstrip <br />
lines by variational conformal mapping technique," IEEE Transactions on Microwave <br />
Theory and Techniques, vol. 36, no. 3, pp. 576-581, Mar. 1988, doi: 10.1109/22.3551.<br />
<br />
[31] C. Shih, R.-B. Wu, S.-K. Jeng, and C. H. Chen, "Frequency-dependent characteristics <br />
of open microstrip lines with finite strip thickness," IEEE Transactions on Microwave <br />
Theory and Techniques, vol. 37, no. 4, pp. 793-795, April 1989, doi: 10.1109/22.18856.<br />
<br />
[32] C. –N. Chang, Y. –C. Wong, and C. H. Chen, "Full-wave analysis of coplanar <br />
waveguides by variational conformal mapping technique," IEEE Transactions on <br />
Microwave Theory and Techniques, vol. 38, no. 9, pp. 1339 - 1344, Sep. 1990, doi: <br />
10.1109/22.58662.<br />
<br />
[33] C. –N. Chang, W. –C. Chang, and C. H. Chen, "Full-wave analysis of multilayer <br />
coplanar lines," IEEE Transactions on Microwave Theory and Techniques, vol. 39, no. <br />
4, pp. 747 - 750, April 1991, doi: 10.1109/22.76444.<br />
|submitted=No<br />
}}</div>Administrator1http://ieeemilestones.ethw.org/index.php?title=Milestone-Proposal:Theoretical_Foundation_of_Finite-Theoretical_Foundation_of_Finite-Element-Method_for_Electromagnetics&diff=11163Milestone-Proposal:Theoretical Foundation of Finite-Theoretical Foundation of Finite-Element-Method for Electromagnetics2021-06-15T13:39:02Z<p>Administrator1: Administrator1 moved page Milestone-Proposal:Theoretical Foundation of Finite-Theoretical Foundation of Finite-Element-Method for Electromagnetics to Milestone-Proposal:Theoretical Foundation of Finite-Element-Method for Electromagnetics</p>
<hr />
<div>#REDIRECT [[Milestone-Proposal:Theoretical Foundation of Finite-Element-Method for Electromagnetics]]</div>Administrator1http://ieeemilestones.ethw.org/index.php?title=Milestone-Proposal:Theoretical_Foundation_of_Finite-Element-Method_for_Electromagnetics&diff=11157Milestone-Proposal:Theoretical Foundation of Finite-Element-Method for Electromagnetics2021-06-14T14:41:34Z<p>Administrator1: </p>
<hr />
<div>{{Proposal<br />
|docketid=2021-12<br />
|litigation=No<br />
|more than 25 years=Yes<br />
|within fields of interest=Yes<br />
|benefit to humanity=Yes<br />
|regional importance=Yes<br />
|ou is paying=Yes<br />
|ou is arranging dedication=Yes<br />
|section is taking responsibility for plaque=Yes<br />
|a11=Yes<br />
|a3=1979 -1991<br />
|a1=Theoretical Foundation of Finite-Element-Method for Electromagnetics<br />
|plaque citation=From 1979 to 1991, an electromagnetic-wave research group in the department of electrical <br />
engineering, National Taiwan University, laid the theoretical foundation for the Finite Element <br />
Method for general linear Electromagnetic field problems. They also found a straightforward<br />
derivation as a generalized Galerkin's method. It has been widely applied in academic <br />
researches and commercial software development, like the early versions of HFSS.<br />
<br />
1979 至 1991 期間，台大電機系的電波研究團隊建構了應用於一般線性電磁學問題的有限元素<br />
法理論基礎。他們也發現有限元素法的矩陣方程式，可以由推廣的 Galerkin 方法直接完成。這種<br />
推廣的 Galerkin 方法很快就應用到許多學術研究以及廣為應用的商業模擬軟體開發，如 HFSS。<br />
|a2b=IEEE Taipei Section<br />
|IEEE units paying={{IEEE Organizational Unit Paying<br />
|Unit=IEEE Taipei Section<br />
|Senior officer name=Kea-Tiong Tang, Chairman<br />
}}<br />
|IEEE units arranging={{IEEE Organizational Unit Arranging<br />
|Unit=IEEE Taipei Section<br />
|Senior officer name=Kea-Tiong Tang, Chairman<br />
}}<br />
|IEEE sections monitoring={{IEEE Section Monitoring<br />
|Section=IEEE Taipei Section<br />
|Section chair name=Kea-Tiong Tang, Chairman<br />
}}<br />
|Milestone proposers={{Milestone proposer<br />
|Proposer name=Shyh-Kang Jeng, Ruey-Beei Wu, and Jin-Fa Lee<br />
|Proposer email=skjeng@ntu.edu.tw, rbwu@ntu.edu.tw, and jin.fa.lee.1863@gmail.com<br />
}}<br />
|a2a=Department of Electrical Engineering, National Taiwan University, 1, Sec. 4, Roosevelt Rd., Taipei, Taiwan 10617. GPS coordinates: x 25.01953, y 121.54410<br />
|a7=The intended site is inside the main department building, which started its construction when Professor Chun Hsiung Chen, the team leader for the proposed milestone, served as the department head from 1982 to 1985. In this building, Professor Chen and his students in the team taught and developed further applications of the milestone. However, the major works of the proposed milestone were conducted earlier in the now civil engineering building, about 600 meters away. This building now accommodates more than 2500 students, including 800 undergraduates, 1200 master, and 500 Ph.D. students, reside to study various areas in electrical engineering. It is the "powerhouse" in Taiwan to promote the innovation, education, and promotion of electrical engineering for humanity.<br />
|a8=The original buildings where the development took place now serve a different goal, are no longer publicly accessible, and will probably be demolished within a few years.<br />
|mounting details=[[image:Varational electromagnetics plaque.jpg|thumb]] The intended location is near the entrance of the auditorium in the building, where the seminars, conferences, and invited lectures are frequently held. A picture giving an overview of the entrance of the auditorium is shown below. The IEEE can consult the department of Electrical Engineering about the exact place and mounting within the building<br />
|a9=The building is opened on weekdays. The site is protected/secured by a management team and security cameras.<br />
|a10=Chairman Chung-Chih Wu, Department of Electrical Engineering, National Taiwan University<br />
|a4=The Finite-Element Method (FEM) has been popular in modeling linear electromagnetic fields, <br />
from radiation, scattering, waveguide, to high-frequency circuits. To get a matrix equation for <br />
FEM, we have to derive a variational equation first. The applications of finite element methods <br />
for static fields were understood, and the variational nature of the formulation was well <br />
documented. However, for electromagnetic wave radiations and scattering problems, the <br />
underlying physics is non-Hermitian, and the corresponding variational principle was lacking in <br />
the 1980s. <br />
<br />
Consequently, the work's significance is: proposing a systematic method for derivation of <br />
variational equations, including exterior fields in the variational equations, and discovering a <br />
shortcut for deriving the FEM matrix equations directly. The inclusion of exterior field results in <br />
the popularity of the hybrid element method, and the shortcut method was a generalized <br />
Galerkin's method. Such a shortcut and the hybrid finite element method have been widely <br />
used for academic research and successful commercial software development, like the early <br />
versions of HFSS software (High-Frequency Structure Simulation).<br />
|a6=The major obstacles needed to be overcome by the FEM team led by Professor Chun Hsiung <br />
Chen (FEM@NTU) are: difficulty in treating non-self-adjoint fields, unsystematic methods for <br />
the variational formulation, difficulty in dealing with exterior fields, difficulty to find physical <br />
interpretation, tedious approaches for obtaining the FEM matrix equations, and challenge to <br />
prove that the proposed shortcut method is consistent with the proposed fundamental<br />
variational equation.<br />
<br />
'''Difficulty in Treating Non-self-adjoint fields'''<br />
<br />
Before 1980, most papers about variational formulation assume that the problem as an operator <br />
equation together with boundary conditions is self-adjoint. The inner product of a field with an <br />
operator operated on another field with associated boundary conditions is the same if we switch <br />
positions of the field and the operator. This reciprocity does not hold for a non-self-adjoint <br />
problem. For an example of the non-self-adjoint problem, consider the situation with <br />
anisotropic materials whose characteristics are described by non-symmetric and/or non-Hermitian matrices. <br />
<br />
The FEM@NTU team in 1980 first proposed a general variational formulation with an adjoint <br />
problem to handle a non-self-adjoint problem. The solution of the adjoint problem is related <br />
to problems with the material characteristics being the transpose or Hermitian of those of the <br />
original problem. Although the adjoint field is introduced, we still need to solve only the field <br />
distribution of the original problem with the FEM. The 1980 paper also provided physical <br />
interpretation through a concept of generalized reaction. However, it did not reveal how to <br />
extend the formulation for general exterior problems.<br />
<br />
'''Unsystematic derivation of variational formulation'''<br />
<br />
For mechanics, a variational equation is often obtained from the least action principle. For <br />
electromagnetics, the application of the FEM for exterior field problems is scarce before 1984.<br />
The most related papers are: Silvester and Hsieh (1971) [1], McDonald and Wexler (1972) [2], <br />
the Unimoment method (Mei, 1974) [3], and Morishita and Kumagai (1977) [4]. The variational <br />
equations in these works are derived case by case after setting up systems of partial differential <br />
equations from the Maxwell equation, except for Morishita and Kumagai in 1977, in which the <br />
formulation started from the least action principle generalized for electromagnetic fields. <br />
However, their approach is inconvenient and indirect for use since the formulation involves <br />
vector and scalar potentials.<br />
The FEM@NTU team first proposed in 1980 (primarily for interior problems and simple one-dimensional problems) [5] and 1984 (with extension to general exterior problems) [6] that the <br />
FEM equations for any linear Electromagnetic field problems can be deduced from setting the <br />
Fundamental Variational Principle (FVP) to be stationary, equivalent to the Maxwell equations<br />
along with the associated boundary conditions. Variational equations can be deduced simply <br />
by applying problem-dependent constraints to reduce the FVP. <br />
<br />
'''Difficulty in Dealing with Exterior Fields'''<br />
<br />
Silvester and Hsieh [1] applied Green's theorem to obtain a variational equation by treating the <br />
outer region as a single exterior element. However, they dealt with only 2D Laplace equations, <br />
i.e., static fields only. McDonald and Wexler [2] treated an Integral equation as a constraint to <br />
replace the exterior element. Their paper also shows that they can handle only 2-D Poisson <br />
equations, again, static fields only. Mei [3] proposed the unimoment method. He imposed an <br />
artificial boundary and expressed the exterior and interior fields as sums of eigenmodes and <br />
pseudo modes, respectively. A pseudo mode for the internal problem was obtained by the FEM <br />
with enforcing boundary conditions on the artificial boundary like an exterior eigenmode. The coefficients of both series were then acquired by matching the continuity conditions on the <br />
artificial boundary. The exterior field was not included in the variational equations directly.<br />
<br />
The FEM@NTU team expressed the exterior field in the following ways: a sum of eigenmodes <br />
(including scattering wave modes [6] and propagation modes in general waveguide [7]) or an <br />
integral over the artificial interior-exterior boundary [8]. Such expressions are then included<br />
in the functional with careful treatment for keeping their stationarity. In addition, the <br />
FEM@NTU team also proposed an attractive approach for dielectric waveguide problems. For <br />
such problems, 2-D transverse trial fields extending to infinity in the stationary functional are <br />
transformed into the inside of a closed region in the complex plane by a conformal mapping<br />
[9]. The exterior fields are thus taken into considerations automatically.<br />
<br />
'''Difficulty to Find Physical interpretation'''<br />
<br />
Many early publications about variational formulation describe their results with mathematic <br />
manipulation only. The variational principles derived by the FEM@NTU team in 1980 [5] and <br />
1984 [6] were with a physical interpretation of general reaction. Note also the stationarity of <br />
the FVP is equivalent to the Maxwell equations along with the boundary conditions, just like <br />
that the principle of virtual work is equivalent to Newton's laws in statics and dynamics. Also,<br />
in the 1984 paper [6], the FVP can be reduced to a form as oscillatory power if the problem is <br />
self-adjoint, which is similar to the least action principle for mechanics.<br />
<br />
'''Tedious Approaches for Obtaining the FEM matrix equations'''<br />
<br />
The process of obtaining a FEM matrix equation from the FVP by applying problem-related <br />
constraints and the Ritz procedure are pretty tedious, though systematic. The FEM@NTU <br />
team's 1985 paper introduced the Variational Reaction Theory (VRT) [10] to derive the required <br />
matrix equation and found it a generalization of the conventional Galerkin's method. <br />
<br />
'''Difficulty in Proving the Shortcut Being Consistent with the Fundamental Variational Equation'''<br />
<br />
The stationarity of the FVP proposed in 1984 [6] is equivalent to the Maxwell equations and <br />
should hold for all linear electromagnetic field problems. The VRT [10] is more efficient in <br />
deriving the required FEM matrix equations. However, its consistency with the variational <br />
equation of FVP was not clear. In other words, why does the generalized Galerkin's method <br />
work? Why does the way to deal with the exterior field in the generalized Galerkin's method <br />
lead to the correct solution? Such essential theoretical questions were answered in a FEM@NTU <br />
paper in 1988, in which the team proposed the concept of the Partial Variational Principle (PVP) <br />
[11]. By PVP, the variation on a functional of trial field f and its adjoint f<sup>a</sup>, like the partial <br />
differentiation, equals the sum of two functionals (PVPs), where one is obtained by taking partial <br />
variation with respect to f while the other is taken with respect to f<sup>a</sup>. If only field f is to be solved, <br />
the functional by taking partial variation to f can be ignored. The resultant partial variational <br />
principle is just the same as the starting equation of VRT. The consistency of VRT and the <br />
variational equation on the FVP is thus proved.<br />
|a5=Features of this series of work are given below:<br />
#First variational formulation equivalent to the Maxwell equations and associated boundary conditions. Also proposed are their physical interpretations.<br />
#A systematic approach to derive the FEM matrix equations.<br />
#First inclusion of exterior field in the variational equation, which leads to the now popular hybrid finite element method.<br />
#First shortcut to derive the FEM matrix equations directly, which is equivalent to a generalized Galerkin's method and widely used in academic and commercial software development circles.<br />
#A conformal mapping technique for dielectric waveguide problems to transform the two-dimensional transverse field into the inside of a closed region. Solving the fields in this closed region by the FEM handles the exterior fields automatically.<br />
<br />
'''Later development'''<br />
<br />
Since the FEM@NTU team published their 1985 papers, the generalized Galerkin's method <br />
becomes very popular in solving the scattering of objects in free space and waveguide <br />
structures. The primarily related papers are those introducing the transfinite element method <br />
(Lee and Cendes, 1987, 1987 [12], [13]; Cendes and Lee, 1988 [14]; Lee, Sun, and Cendes, 1991<br />
[15]), and those emphasizing hybrid finite element methods for the scattering of objects in free <br />
space (Jin and Liepa, 1988 [16]; Jin and Liepa, 1988 [17]). The transfinite element method was <br />
then applied for developing the commercial software HFSS for dealing with RF, microwave, and <br />
millimeter-wave circuits. The hybrid finite element method has also been proved efficient and <br />
effective in solving realistic scattering problems (for example, Jin and Volakis, 1991 [18] and <br />
Shen et al., 1998 [19]). However, the impact of the generalized Galerkin's method is not limited <br />
by its applications to solving electromagnetic wave problems with the finite element methods. <br />
Professor Jin-Fa Lee at the Ohio State University also recognized the strong correlation of the <br />
generalized Galerkin's method with the reciprocity theorem in electromagnetic fields and the <br />
popular Bi-CG methods for solving complex symmetric but non-Hermitian matrices equations.<br />
<br />
'''The FEM@NTU team'''<br />
<br />
The FEM@NTU leader, Professor Chen, is the first faculty in Taiwan who published papers in <br />
IEEE journals (as early as 1970 [20]). He and his students published their first FEM paper on <br />
applying the FEM to a one-dimensional problem with inhomogeneous dielectric in free space <br />
in 1979 [21], [22] and a rectangular waveguide in 1981 [23]. Later the FEM@NTU team began <br />
to focus on finding a general variational equation for electromagnetic field problems. They <br />
published papers on the fundamental variational principles (FVP) in 1980 [5] and 1984 [6], <br />
respectively. A shortcut, the VRT, for deriving FEM matrix equations from the FVP was then <br />
proposed in their 1985 paper [10]. Finally, in 1988, the FEM@NTU team proposed the partial <br />
variational principle [11] and proved that the VRT is consistent with the variational equation on <br />
the FVP.<br />
<br />
Not restricted to pure and abstract mathematic formulation, based on the FVP, VRT, and PVP, <br />
Professor Chen and his students published various applications. The applications include: the <br />
scattering of the perfect electric conductor (PEC) cylinder with inhomogeneous dielectric <br />
coating [6], general scattering from anisotropic inhomogeneous slabs [24], [25] and cylinders<br />
[26], scattering from a magnetostatic slab in parallel-plate waveguide [7], general analysis of <br />
dielectric waveguides [8], [10], birefringence analysis of anisotropic optical fibers [27], and <br />
analysis of discontinuities in a dielectric waveguide [11] and planar dielectric waveguides [28], <br />
and planar dielectric antennas [29], For weakly guiding dielectric waveguides [9], microstrip lines<br />
[30], [31], and coplanar waveguides [32], [33], the FEM@NTU team conceived a delicate idea, <br />
the Variational Conformal Mapping technique [9], to transform the problem onto a complex <br />
plane, and wherein solve a scalar field.<br />
<br />
'''Further information'''<br />
<br />
Jin-Fa Lee is the major developer of the booming commercial software HFSS. He took <br />
Professor Chen's course on mathematical physics, which introduced variational formulation <br />
coupled with the FEM in 1981 when he was an undergraduate student in the National Taiwan <br />
University's electric engineering department. Afterward, he pursued his Ph.D. studies at<br />
Carnegie Mellon University under the supervision of Professor Zoltan J. Cendes, father of HFSS <br />
and the founder of Ansoft Corp. Note Ansoft Corp. was later acquired by Ansys Corp.<br />
|references='''1. General variational principle for interior field problems and simple one-dimensional <br />
transmission-reflection problems'''<br />
<br />
The work [5] is included as a reference in Chapter 6, Variational Principles for Electromagnetics, <br />
The Finite Element Method in Electromagnetics, by Jianming Jin, New York, USA: John Wiley & <br />
Sons, Inc., 1993, a popular textbook for learning the FEM for electromagnetics. In that chapter, <br />
Professor Jin commented on the use of variational equations as: "It is only in recent years that <br />
the variational formulation has been discussed more extensively, mainly to satisfy the need for <br />
finite element method … However, even these methods remain unknown to many researchers <br />
and generally are not taught to graduate students. This situation is in contrast to that of <br />
Galerkin's method, which is a popular choice both in research and instruction, possibly because <br />
of its simplicity."<br />
<br />
We agree that starting the FEM with a general variational formulation requires much<br />
mathematical background, and its derivation is not as straightforward as the generalized <br />
Galerkin's method. However, the FEM@NTU team also found this shortcut [10] and provided <br />
it with a more rigorous theoretical foundation [11].<br />
<br />
Jin also said: "If we indeed establish a general procedure to derive the variational formulation <br />
for any given problem, there will be no major obstacles, except for personal preference, to <br />
prevent us from employing the variational method for the finite element formulation." Here Jin <br />
skipped our general variational equation of FVP, which could be due to the abstract <br />
mathematics in the FEM@NTU work [6], especially in including the exterior field into the <br />
variational equation. Actually, in Jin's book, the functional given is derived from the <br />
generalized Galerkin's method while fine-tuning some boundary terms to ensure that the <br />
functional is stationary.<br />
<br />
Another book, Finite Elements for Wave Electromagnetics: Method and Techniques edited by <br />
Peter P. Silvester and Giuseppe Pelosi, New York, USA: IEEE Press, 1994, collected papers <br />
important to applications of the FEM to electromagnetics. The FEM@NTU contributions [5]<br />
about the general variational formulation and [25] about the VRT were included.<br />
<br />
'''2. Fundamental Variational Principle (FVP) and inclusion of exterior field as hybrid finite <br />
element method'''<br />
<br />
The FVP was proposed in 1984 [6]. It has been applied to model the scattering matrix <br />
coefficients for microwave circuit elements, such as [7]. The transfinite element method in [14] <br />
used a similar approach, though the FEM matrix equations are obtained from the generalized <br />
Galerkin's method. <br />
<br />
A similar approach with another hybrid finite element method for dielectric waveguide analysis<br />
was utilized by Su [8], also Professor Chun Hsiung Chen's student.<br />
<br />
Such a hybrid finite element method for scattering problems was a contribution of Jin [16].<br />
<br />
'''3. Variational Reaction Theory (VRT) as a generalized Glerkin's method'''<br />
<br />
As mentioned above, the VRT [10] became a popular shortcut as a generalized Galerkin's <br />
method in deriving equations for FEM. A lot of published FEM works were based on this <br />
approach. One typical example is applying the VRT to arbitrary two-dimensional <br />
electromagnetic problems with general anisotropic material [26]. Based on a unified (E_z, H_z)<br />
formulation, the scattering problem when a plane wave is obliquely incident upon an <br />
inhomogeneous and anisotropic dielectric cylinder. The variational equation is then derived <br />
with all the exterior problem absorbed into the boundary operator and then solved by the finite <br />
element method. The scattering cross sections of radiation problems can be obtained. In <br />
addition, the guiding problems of dielectric waveguides are also solved by considering <br />
obliquely incident inhomogeneous waves.<br />
<br />
'''4. Partial Variational Principle to connect the VRT and the FVP and its applications to the <br />
analysis of discontinuities in dielectric waveguides'''<br />
<br />
This is the topic of the FEM@NTU paper in 1988 [11]. Its two further similar applications are <br />
published in 1989 [28] and 1990 [29]. <br />
<br />
'''5. Variational Conformal Mapping Techniques'''<br />
<br />
The 1986 paper of the FEM@NTU proposed such an idea in [9] for dielectric waveguide <br />
problems. Because it applied a clever idea to map the scalar potentials in the transverse plane <br />
into the complex plane. The original exterior field distribution is now in a closed region and can <br />
be solved easily by the FEM. With such a technique, problems with edge singularities like the <br />
microstrip and coplanar waveguide propagation problems can also be taken care of easily. <br />
References [30]-[33] are good examples.<br />
<br />
[1] P. Silvester and M.-S. Hsieh, "Finite-element solution of 2-dimensional exterior-field <br />
problems," Proceedings of the Institution of Electrical Engineers, vol. 118, no. 12, pp. <br />
1743 – 1747, 1971. doi: 10.1049/piee.1971.0320<br />
<br />
[2] B. H. McDonald and A. Wexler, "Finite-element solution of unbounded field problems," <br />
IEEE Transactions on Microwave Theory and Techniques, vol. 20, no. 12, pp. 841-<br />
847, Dec. 1972. doi: 10.1109/TMTT.1972.1127895.<br />
<br />
[3] K. Mei, "Unimoment method of solving antenna and scattering problems," IEEE <br />
Transactions on Antennas and Propagation, vol. 22, no. 6, pp. 760-766, Nov. 1974. <br />
doi: 10.1109/TAP.1974.1140894.<br />
<br />
[4] K. Morishita and N. Kumagai, "Unified approach to the derivation of variational <br />
expression for electromagnetic fields," IEEE Transactions on Microwave Theory and <br />
Techniques, vol. 25, no. 1, pp. 34-40, Jan. 1977. doi: 10.1109/TMTT.1977.1129027.<br />
<br />
[5] C. H. Chen and C.-D. Lien, "The variational principle for non-self-adjoint<br />
electromagnetic problems," IEEE Transactions on Microwave Theory and Techniques, <br />
vol. MTT-28, no. 8, pp. 878-886, Aug. 1980. doi: 10.1109/TMTT.1980.1130186.<br />
<br />
[6] S.-K. Jeng and C. H. Chen, "On variational electromagnetics: Theory and application,"<br />
IEEE Transactions on Antennas and Propagation, vol. AP-32, no. 9, pp. 902-907, Sept.<br />
1984. doi: 10.1109/TAP.1984.1143439<br />
<br />
[7] H.-C. Chang, S.-K. Jeng, R.-B. Wu, and C. H. Chen," Propagation of waves through <br />
magnetoplasma slab within a parallel-plate guide," IEEE Transactions on Microwave <br />
Theory and Techniques, vol. MTT-34, no. 1, pp. 50-54. Jan. 1986, doi: 10.1109/8.1074<br />
<br />
[8] C.-C. Su, "A combined method for dielectric waveguides using the finite-element <br />
technique and surface integral equations method," IEEE Transactions on Microwave <br />
Theory and Techniques, vol. MTT-34, no. 11, pp. 1140-1146, Nov. 1986. doi: 10.1109/<br />
TMTT.1986.1133511<br />
<br />
[9] R.-B. Wu and C. H. Chen, "A scalar variational conformal mapping technique for weakly <br />
guiding dielectric waveguides," IEEE Journal of Quantum Electronics, vol. QE-22, no. <br />
3, 1986, pp. 603-609. doi: 10.1109/JQE.1986.1073014<br />
<br />
[10] R.-B. Wu and C. H. Chen, "On the variational reaction theory for dielectric <br />
waveguides," IEEE Transactions on Microwave Theory and Techniques, vol. MTT-33, <br />
no. 6, pp. 477-483, June 1985. doi: 10.1109/TMTT.1985.1133102<br />
<br />
[11] S.-J. Chung and C. H. Chen, "Partial variational principle for electromagnetic field <br />
problems: Theory and applications," IEEE Transactions on Microwave Theory and <br />
Techniques, vol. MTT-36, no. 3, pp. 473-479, Mar. 1988. doi: 10.1109/22.3537<br />
<br />
[12] J.‐F. Lee and Z. J. Cendes, "Transfinite elements: A highly efficient procedure for <br />
modeling open field problems," Journal of Applied Physics 61, 3913 (1987). https:// <br />
doi.org/10.1063/1.338582<br />
The variational formulation in this paper is similar to the one in a FEM@NTU 1982 <br />
paper: S.-K. Jeng and C. H. Chen, "A new variational theory for linear field problems <br />
and its application to electrostatics," Journal of the Chinese Institute of Engineers, vol. <br />
5, no. 2, 1982, pp. 99-107. https://doi.org/10.1080/02533839.1982.9676696<br />
<br />
[13] J.-F. Lee and Z. J. Cendes, "The transfinite element method for computing <br />
electromagnetic scattering from arbitrary lossy cylinders," in 1987 International <br />
Symposium on Antennas and Propagation, pp. 99-102, Jan. 1987, doi: 10.1109/<br />
APS.1987.1150085.<br />
The variational formulation in this paper is similar to the one derived in a FEM@NTU <br />
1984 paper [6].<br />
<br />
[14] Z. J. Cendes and J.-F. Lee, "The transfinite element method for modeling MMIC <br />
devices," IEEE Transactions on Microwave Theory and Techniques, vol. 36, no. 12, <br />
pp. 1639-1649, Dec. 1988. doi: 10.1109/22.17395.<br />
,<br />
<br />
[15] J. F. Lee, D. K. Sun and Z. J. Cendes, "Tangential vector finite elements for <br />
electromagnetic field computation," IEEE Transactions on Magnetics, vol. 27, no. 5, <br />
pp. 4032-4035, Sept. 1991. doi: 10.1109/20.104986.<br />
<br />
[16] J.-M. Jin and V. V. Liepa, "Application of hybrid finite element method to <br />
electromagnetic scattering from coated cylinders," IEEE Transactions on Antennas <br />
and Propagation, vol. 36, no. 1, Jan. 1988, pp. 50-54. doi: 10.1109/8.1074<br />
<br />
[17] J.-M. Jin and V. V. Liepa, "A note on hybrid finite element method for solving scattering <br />
problems," IEEE Transactions on Antennas and Propagation, vol. 36, no. 10, pp. 1486-<br />
1490, Oct. 1988. doi: 10.1109/8.8638.<br />
<br />
[18] J.-M. Jin and J. L. Volakis, "Scattering and radiation from microstrip patch antennas <br />
and arrays residing in a cavity," in 1991 International Symposium on Antennas and <br />
Propagation, pp. 657-660 vol.2. 1991, doi: 10.1109/APS.1991.174925.<br />
<br />
[19] X.-Q. Sheng, J.-M. Jin, J. Song, C.-C. Lu, and W. C. Chew, "On the formulation of <br />
hybrid finite-element and boundary-integral methods for 3-D scattering," IEEE <br />
Transactions on Antennas and Propagation, vol. 46, no. 3, pp. 303-311, March 1998.<br />
doi: 10.1109/8.662648.<br />
<br />
[20] C. H. Chen, "Some remarks on exterior electromagnetic boundary value problems for <br />
spheres," IEEE Transactions on Antennas and Propagation, vol. 18, no. 5, pp. 705-<br />
707, Sept. 1970. doi: 10.1109/TAP.1970.1139747.<br />
<br />
[21] C. H. Chen and C.-D. Lien, "A finite element solution of the wave propagation problem <br />
for an inhomogeneous dielectric slab," IEEE Transactions on Antennas and <br />
Propagation, vol. 27, no. 6, pp. 877-880, Nov. 1979. doi: 10.1109/TAP.1979.1142199.<br />
<br />
[22] C.-H. Chen and Y.-W. Kiang, "A variational theory for wave propagation in a one-dimensional inhomogeneous medium," IEEE Transactions on Antennas and <br />
Propagation, vol. 28, no. 6, pp. 762-769, Nov. 1980. doi: 10.1109/TAP.1980.1142435.<br />
<br />
[23] C.-T. Liu and C. H. Chen, "A variational theory for wave propagation in inhomogeneous <br />
dielectric slab loaded waveguides," IEEE Transactions on Microwave Theory and <br />
Techniques, vol. 29, no. 8, pp. 805-812, Aug. 1981. doi: 10.1109/TMTT.1981.1130451.<br />
<br />
[24] S.-K. Jeng and C. H. Chen, "Variational finite element solution of electromagnetic wave <br />
propagation in a one‐dimensional inhomogeneous anisotropic medium," Journal of <br />
Applied Physics 55, 630, 1984. https://doi.org/10.1063/1.333115<br />
<br />
[25] S.-K. Jeng, R.-B. Wu and C. H. Chen, "Waves obliquely incident upon a stratified <br />
anisotropic slab: A variational reaction approach," Radio Science, vol. 21, no. 4, pp. <br />
681-688, July-Aug. 1986, doi: 10.1029/RS021i004p00681.<br />
<br />
[26] R.-B. Wu and C. H. Chen, "Variational reaction formulation of scattering problem for <br />
anisotropic dielectric cylinders," IEEE Transactions on Antennas and Propagation, vol. <br />
34, no. 5, pp. 640-645, May 1986, doi: 10.1109/TAP.1986.1143874.<br />
<br />
[27] R.-B. Wu and C. H. Chen, "Birefringence analysis of anisotropic optical fibers using <br />
variational reaction theory," IEEE Transactions on Microwave Theory and Techniques, <br />
vol. 34, no. 6, pp. 741-745, June 1986, doi: 10.1109/TMTT.1986.1133428.<br />
<br />
[28] S.-J. Chung and C. H. Chen, "A partial variational approach for arbitrary discontinuities <br />
in planar dielectric waveguides," IEEE Transactions on Microwave Theory and <br />
Techniques, vol. MTT-37, no. 1, pp. 208 - 214, Jan. 1989. doi: 10.1109/22.20040<br />
<br />
[29] S.-J. Chung and C. H. Chen, "A partial variational analysis of planar dielectric <br />
antennas," IEEE Transactions on Antennas and Propagation, vol. 39, no. 6, pp. 713 -<br />
718, Jun. 1991. doi: 10.1109/8.86867<br />
<br />
[30] C. Shih, R. -B. Wu, S.-K. Jeng, and C. H. Chen, "A full-wave analysis of microstrip <br />
lines by variational conformal mapping technique," IEEE Transactions on Microwave <br />
Theory and Techniques, vol. 36, no. 3, pp. 576-581, Mar. 1988, doi: 10.1109/22.3551.<br />
<br />
[31] C. Shih, R.-B. Wu, S.-K. Jeng, and C. H. Chen, "Frequency-dependent characteristics <br />
of open microstrip lines with finite strip thickness," IEEE Transactions on Microwave <br />
Theory and Techniques, vol. 37, no. 4, pp. 793-795, April 1989, doi: 10.1109/22.18856.<br />
<br />
[32] C. –N. Chang, Y. –C. Wong, and C. H. Chen, "Full-wave analysis of coplanar <br />
waveguides by variational conformal mapping technique," IEEE Transactions on <br />
Microwave Theory and Techniques, vol. 38, no. 9, pp. 1339 - 1344, Sep. 1990, doi: <br />
10.1109/22.58662.<br />
<br />
[33] C. –N. Chang, W. –C. Chang, and C. H. Chen, "Full-wave analysis of multilayer <br />
coplanar lines," IEEE Transactions on Microwave Theory and Techniques, vol. 39, no. <br />
4, pp. 747 - 750, April 1991, doi: 10.1109/22.76444.<br />
|submitted=No<br />
}}</div>Administrator1http://ieeemilestones.ethw.org/index.php?title=Milestone-Proposal:Theoretical_Foundation_of_Finite-Element-Method_for_Electromagnetics&diff=11155Milestone-Proposal:Theoretical Foundation of Finite-Element-Method for Electromagnetics2021-06-14T14:36:41Z<p>Administrator1: </p>
<hr />
<div>{{Proposal<br />
|litigation=No<br />
|more than 25 years=Yes<br />
|within fields of interest=Yes<br />
|benefit to humanity=Yes<br />
|regional importance=Yes<br />
|ou is paying=Yes<br />
|ou is arranging dedication=Yes<br />
|section is taking responsibility for plaque=Yes<br />
|a11=Yes<br />
|a3=1979 -1991<br />
|a1=Theoretical Foundation of Finite-Element-Method for Electromagnetics<br />
|plaque citation=From 1979 to 1991, an electromagnetic-wave research group in the department of electrical <br />
engineering, National Taiwan University, laid the theoretical foundation for the Finite Element <br />
Method for general linear Electromagnetic field problems. They also found a straightforward<br />
derivation as a generalized Galerkin's method. It has been widely applied in academic <br />
researches and commercial software development, like the early versions of HFSS.<br />
<br />
1979 至 1991 期間，台大電機系的電波研究團隊建構了應用於一般線性電磁學問題的有限元素<br />
法理論基礎。他們也發現有限元素法的矩陣方程式，可以由推廣的 Galerkin 方法直接完成。這種<br />
推廣的 Galerkin 方法很快就應用到許多學術研究以及廣為應用的商業模擬軟體開發，如 HFSS。<br />
|a2b=IEEE Taipei Section<br />
|IEEE units paying={{IEEE Organizational Unit Paying<br />
|Unit=IEEE Taipei Section<br />
|Senior officer name=Kea-Tiong Tang, Chairman<br />
}}<br />
|IEEE units arranging={{IEEE Organizational Unit Arranging<br />
|Unit=IEEE Taipei Section<br />
|Senior officer name=Kea-Tiong Tang, Chairman<br />
}}<br />
|IEEE sections monitoring={{IEEE Section Monitoring<br />
|Section=IEEE Taipei Section<br />
|Section chair name=Kea-Tiong Tang, Chairman<br />
}}<br />
|Milestone proposers={{Milestone proposer<br />
|Proposer name=Shyh-Kang Jeng, Ruey-Beei Wu, and Jin-Fa Lee<br />
|Proposer email=skjeng@ntu.edu.tw, rbwu@ntu.edu.tw, and jin.fa.lee.1863@gmail.com<br />
}}<br />
|a2a=Department of Electrical Engineering, National Taiwan University, 1, Sec. 4, Roosevelt Rd., Taipei, Taiwan 10617. GPS coordinates: x 25.01953, y 121.54410<br />
|a7=The intended site is inside the main department building, which started its construction when Professor Chun Hsiung Chen, the team leader for the proposed milestone, served as the department head from 1982 to 1985. In this building, Professor Chen and his students in the team taught and developed further applications of the milestone. However, the major works of the proposed milestone were conducted earlier in the now civil engineering building, about 600 meters away. This building now accommodates more than 2500 students, including 800 undergraduates, 1200 master, and 500 Ph.D. students, reside to study various areas in electrical engineering. It is the "powerhouse" in Taiwan to promote the innovation, education, and promotion of electrical engineering for humanity.<br />
|a8=The original buildings where the development took place now serve a different goal, are no longer publicly accessible, and will probably be demolished within a few years.<br />
|mounting details=[[image:Varational electromagnetics plaque.jpg|thumb]] The intended location is near the entrance of the auditorium in the building, where the seminars, conferences, and invited lectures are frequently held. A picture giving an overview of the entrance of the auditorium is shown below. The IEEE can consult the department of Electrical Engineering about the exact place and mounting within the building<br />
|a9=The building is opened on weekdays. The site is protected/secured by a management team and security cameras.<br />
|a10=Chairman Chung-Chih Wu, Department of Electrical Engineering, National Taiwan University<br />
|a4=The Finite-Element Method (FEM) has been popular in modeling linear electromagnetic fields, <br />
from radiation, scattering, waveguide, to high-frequency circuits. To get a matrix equation for <br />
FEM, we have to derive a variational equation first. The applications of finite element methods <br />
for static fields were understood, and the variational nature of the formulation was well <br />
documented. However, for electromagnetic wave radiations and scattering problems, the <br />
underlying physics is non-Hermitian, and the corresponding variational principle was lacking in <br />
the 1980s. <br />
<br />
Consequently, the work's significance is: proposing a systematic method for derivation of <br />
variational equations, including exterior fields in the variational equations, and discovering a <br />
shortcut for deriving the FEM matrix equations directly. The inclusion of exterior field results in <br />
the popularity of the hybrid element method, and the shortcut method was a generalized <br />
Galerkin's method. Such a shortcut and the hybrid finite element method have been widely <br />
used for academic research and successful commercial software development, like the early <br />
versions of HFSS software (High-Frequency Structure Simulation).<br />
|a6=The major obstacles needed to be overcome by the FEM team led by Professor Chun Hsiung <br />
Chen (FEM@NTU) are: difficulty in treating non-self-adjoint fields, unsystematic methods for <br />
the variational formulation, difficulty in dealing with exterior fields, difficulty to find physical <br />
interpretation, tedious approaches for obtaining the FEM matrix equations, and challenge to <br />
prove that the proposed shortcut method is consistent with the proposed fundamental<br />
variational equation.<br />
<br />
'''Difficulty in Treating Non-self-adjoint fields'''<br />
<br />
Before 1980, most papers about variational formulation assume that the problem as an operator <br />
equation together with boundary conditions is self-adjoint. The inner product of a field with an <br />
operator operated on another field with associated boundary conditions is the same if we switch <br />
positions of the field and the operator. This reciprocity does not hold for a non-self-adjoint <br />
problem. For an example of the non-self-adjoint problem, consider the situation with <br />
anisotropic materials whose characteristics are described by non-symmetric and/or non-Hermitian matrices. <br />
<br />
The FEM@NTU team in 1980 first proposed a general variational formulation with an adjoint <br />
problem to handle a non-self-adjoint problem. The solution of the adjoint problem is related <br />
to problems with the material characteristics being the transpose or Hermitian of those of the <br />
original problem. Although the adjoint field is introduced, we still need to solve only the field <br />
distribution of the original problem with the FEM. The 1980 paper also provided physical <br />
interpretation through a concept of generalized reaction. However, it did not reveal how to <br />
extend the formulation for general exterior problems.<br />
<br />
'''Unsystematic derivation of variational formulation'''<br />
<br />
For mechanics, a variational equation is often obtained from the least action principle. For <br />
electromagnetics, the application of the FEM for exterior field problems is scarce before 1984.<br />
The most related papers are: Silvester and Hsieh (1971) [1], McDonald and Wexler (1972) [2], <br />
the Unimoment method (Mei, 1974) [3], and Morishita and Kumagai (1977) [4]. The variational <br />
equations in these works are derived case by case after setting up systems of partial differential <br />
equations from the Maxwell equation, except for Morishita and Kumagai in 1977, in which the <br />
formulation started from the least action principle generalized for electromagnetic fields. <br />
However, their approach is inconvenient and indirect for use since the formulation involves <br />
vector and scalar potentials.<br />
The FEM@NTU team first proposed in 1980 (primarily for interior problems and simple one-dimensional problems) [5] and 1984 (with extension to general exterior problems) [6] that the <br />
FEM equations for any linear Electromagnetic field problems can be deduced from setting the <br />
Fundamental Variational Principle (FVP) to be stationary, equivalent to the Maxwell equations<br />
along with the associated boundary conditions. Variational equations can be deduced simply <br />
by applying problem-dependent constraints to reduce the FVP. <br />
<br />
'''Difficulty in Dealing with Exterior Fields'''<br />
<br />
Silvester and Hsieh [1] applied Green's theorem to obtain a variational equation by treating the <br />
outer region as a single exterior element. However, they dealt with only 2D Laplace equations, <br />
i.e., static fields only. McDonald and Wexler [2] treated an Integral equation as a constraint to <br />
replace the exterior element. Their paper also shows that they can handle only 2-D Poisson <br />
equations, again, static fields only. Mei [3] proposed the unimoment method. He imposed an <br />
artificial boundary and expressed the exterior and interior fields as sums of eigenmodes and <br />
pseudo modes, respectively. A pseudo mode for the internal problem was obtained by the FEM <br />
with enforcing boundary conditions on the artificial boundary like an exterior eigenmode. The coefficients of both series were then acquired by matching the continuity conditions on the <br />
artificial boundary. The exterior field was not included in the variational equations directly.<br />
<br />
The FEM@NTU team expressed the exterior field in the following ways: a sum of eigenmodes <br />
(including scattering wave modes [6] and propagation modes in general waveguide [7]) or an <br />
integral over the artificial interior-exterior boundary [8]. Such expressions are then included<br />
in the functional with careful treatment for keeping their stationarity. In addition, the <br />
FEM@NTU team also proposed an attractive approach for dielectric waveguide problems. For <br />
such problems, 2-D transverse trial fields extending to infinity in the stationary functional are <br />
transformed into the inside of a closed region in the complex plane by a conformal mapping<br />
[9]. The exterior fields are thus taken into considerations automatically.<br />
<br />
'''Difficulty to Find Physical interpretation'''<br />
<br />
Many early publications about variational formulation describe their results with mathematic <br />
manipulation only. The variational principles derived by the FEM@NTU team in 1980 [5] and <br />
1984 [6] were with a physical interpretation of general reaction. Note also the stationarity of <br />
the FVP is equivalent to the Maxwell equations along with the boundary conditions, just like <br />
that the principle of virtual work is equivalent to Newton's laws in statics and dynamics. Also,<br />
in the 1984 paper [6], the FVP can be reduced to a form as oscillatory power if the problem is <br />
self-adjoint, which is similar to the least action principle for mechanics.<br />
<br />
'''Tedious Approaches for Obtaining the FEM matrix equations'''<br />
<br />
The process of obtaining a FEM matrix equation from the FVP by applying problem-related <br />
constraints and the Ritz procedure are pretty tedious, though systematic. The FEM@NTU <br />
team's 1985 paper introduced the Variational Reaction Theory (VRT) [10] to derive the required <br />
matrix equation and found it a generalization of the conventional Galerkin's method. <br />
<br />
'''Difficulty in Proving the Shortcut Being Consistent with the Fundamental Variational <br />
Equation'''<br />
<br />
The stationarity of the FVP proposed in 1984 [6] is equivalent to the Maxwell equations and <br />
should hold for all linear electromagnetic field problems. The VRT [10] is more efficient in <br />
deriving the required FEM matrix equations. However, its consistency with the variational <br />
equation of FVP was not clear. In other words, why does the generalized Galerkin's method <br />
work? Why does the way to deal with the exterior field in the generalized Galerkin's method <br />
lead to the correct solution? Such essential theoretical questions were answered in a FEM@NTU <br />
paper in 1988, in which the team proposed the concept of the Partial Variational Principle (PVP) <br />
[11]. By PVP, the variation on a functional of trial field f and its adjoint f<sup>a</sup>, like the partial <br />
differentiation, equals the sum of two functionals (PVPs), where one is obtained by taking partial <br />
variation with respect to f while the other is taken with respect to f<sup>a</sup>. If only field f is to be solved, <br />
the functional by taking partial variation to f can be ignored. The resultant partial variational <br />
principle is just the same as the starting equation of VRT. The consistency of VRT and the <br />
variational equation on the FVP is thus proved.<br />
|a5=Features of this series of work are given below:<br />
#First variational formulation equivalent to the Maxwell equations and associated boundary conditions. Also proposed are their physical interpretations.<br />
#A systematic approach to derive the FEM matrix equations.<br />
#First inclusion of exterior field in the variational equation, which leads to the now popular hybrid finite element method.<br />
#First shortcut to derive the FEM matrix equations directly, which is equivalent to a generalized Galerkin's method and widely used in academic and commercial software development circles.<br />
#A conformal mapping technique for dielectric waveguide problems to transform the two-dimensional transverse field into the inside of a closed region. Solving the fields in this closed region by the FEM handles the exterior fields automatically.<br />
<br />
'''Later development'''<br />
<br />
Since the FEM@NTU team published their 1985 papers, the generalized Galerkin's method <br />
becomes very popular in solving the scattering of objects in free space and waveguide <br />
structures. The primarily related papers are those introducing the transfinite element method <br />
(Lee and Cendes, 1987, 1987 [12], [13]; Cendes and Lee, 1988 [14]; Lee, Sun, and Cendes, 1991<br />
[15]), and those emphasizing hybrid finite element methods for the scattering of objects in free <br />
space (Jin and Liepa, 1988 [16]; Jin and Liepa, 1988 [17]). The transfinite element method was <br />
then applied for developing the commercial software HFSS for dealing with RF, microwave, and <br />
millimeter-wave circuits. The hybrid finite element method has also been proved efficient and <br />
effective in solving realistic scattering problems (for example, Jin and Volakis, 1991 [18] and <br />
Shen et al., 1998 [19]). However, the impact of the generalized Galerkin's method is not limited <br />
by its applications to solving electromagnetic wave problems with the finite element methods. <br />
Professor Jin-Fa Lee at the Ohio State University also recognized the strong correlation of the <br />
generalized Galerkin's method with the reciprocity theorem in electromagnetic fields and the <br />
popular Bi-CG methods for solving complex symmetric but non-Hermitian matrices equations.<br />
<br />
'''The FEM@NTU team'''<br />
<br />
The FEM@NTU leader, Professor Chen, is the first faculty in Taiwan who published papers in <br />
IEEE journals (as early as 1970 [20]). He and his students published their first FEM paper on <br />
applying the FEM to a one-dimensional problem with inhomogeneous dielectric in free space <br />
in 1979 [21], [22] and a rectangular waveguide in 1981 [23]. Later the FEM@NTU team began <br />
to focus on finding a general variational equation for electromagnetic field problems. They <br />
published papers on the fundamental variational principles (FVP) in 1980 [5] and 1984 [6], <br />
respectively. A shortcut, the VRT, for deriving FEM matrix equations from the FVP was then <br />
proposed in their 1985 paper [10]. Finally, in 1988, the FEM@NTU team proposed the partial <br />
variational principle [11] and proved that the VRT is consistent with the variational equation on <br />
the FVP.<br />
<br />
Not restricted to pure and abstract mathematic formulation, based on the FVP, VRT, and PVP, <br />
Professor Chen and his students published various applications. The applications include: the <br />
scattering of the perfect electric conductor (PEC) cylinder with inhomogeneous dielectric <br />
coating [6], general scattering from anisotropic inhomogeneous slabs [24], [25] and cylinders<br />
[26], scattering from a magnetostatic slab in parallel-plate waveguide [7], general analysis of <br />
dielectric waveguides [8], [10], birefringence analysis of anisotropic optical fibers [27], and <br />
analysis of discontinuities in a dielectric waveguide [11] and planar dielectric waveguides [28], <br />
and planar dielectric antennas [29], For weakly guiding dielectric waveguides [9], microstrip lines<br />
[30], [31], and coplanar waveguides [32], [33], the FEM@NTU team conceived a delicate idea, <br />
the Variational Conformal Mapping technique [9], to transform the problem onto a complex <br />
plane, and wherein solve a scalar field.<br />
<br />
'''Further information'''<br />
<br />
Jin-Fa Lee is the major developer of the booming commercial software HFSS. He took <br />
Professor Chen's course on mathematical physics, which introduced variational formulation <br />
coupled with the FEM in 1981 when he was an undergraduate student in the National Taiwan <br />
University's electric engineering department. Afterward, he pursued his Ph.D. studies at<br />
Carnegie Mellon University under the supervision of Professor Zoltan J. Cendes, father of HFSS <br />
and the founder of Ansoft Corp. Note Ansoft Corp. was later acquired by Ansys Corp.<br />
|references='''1. General variational principle for interior field problems and simple one-dimensional <br />
transmission-reflection problems'''<br />
<br />
The work [5] is included as a reference in Chapter 6, Variational Principles for Electromagnetics, <br />
The Finite Element Method in Electromagnetics, by Jianming Jin, New York, USA: John Wiley & <br />
Sons, Inc., 1993, a popular textbook for learning the FEM for electromagnetics. In that chapter, <br />
Professor Jin commented on the use of variational equations as: "It is only in recent years that <br />
the variational formulation has been discussed more extensively, mainly to satisfy the need for <br />
finite element method … However, even these methods remain unknown to many researchers <br />
and generally are not taught to graduate students. This situation is in contrast to that of <br />
Galerkin's method, which is a popular choice both in research and instruction, possibly because <br />
of its simplicity."<br />
<br />
We agree that starting the FEM with a general variational formulation requires much<br />
mathematical background, and its derivation is not as straightforward as the generalized <br />
Galerkin's method. However, the FEM@NTU team also found this shortcut [10] and provided <br />
it with a more rigorous theoretical foundation [11].<br />
<br />
Jin also said: "If we indeed establish a general procedure to derive the variational formulation <br />
for any given problem, there will be no major obstacles, except for personal preference, to <br />
prevent us from employing the variational method for the finite element formulation." Here Jin <br />
skipped our general variational equation of FVP, which could be due to the abstract <br />
mathematics in the FEM@NTU work [6], especially in including the exterior field into the <br />
variational equation. Actually, in Jin's book, the functional given is derived from the <br />
generalized Galerkin's method while fine-tuning some boundary terms to ensure that the <br />
functional is stationary.<br />
<br />
Another book, Finite Elements for Wave Electromagnetics: Method and Techniques edited by <br />
Peter P. Silvester and Giuseppe Pelosi, New York, USA: IEEE Press, 1994, collected papers <br />
important to applications of the FEM to electromagnetics. The FEM@NTU contributions [5]<br />
about the general variational formulation and [25] about the VRT were included.<br />
<br />
'''2. Fundamental Variational Principle (FVP) and inclusion of exterior field as hybrid finite <br />
element method'''<br />
<br />
The FVP was proposed in 1984 [6]. It has been applied to model the scattering matrix <br />
coefficients for microwave circuit elements, such as [7]. The transfinite element method in [14] <br />
used a similar approach, though the FEM matrix equations are obtained from the generalized <br />
Galerkin's method. <br />
<br />
A similar approach with another hybrid finite element method for dielectric waveguide analysis<br />
was utilized by Su [8], also Professor Chun Hsiung Chen's student.<br />
<br />
Such a hybrid finite element method for scattering problems was a contribution of Jin [16].<br />
<br />
'''3. Variational Reaction Theory (VRT) as a generalized Glerkin's method'''<br />
<br />
As mentioned above, the VRT [10] became a popular shortcut as a generalized Galerkin's <br />
method in deriving equations for FEM. A lot of published FEM works were based on this <br />
approach. One typical example is applying the VRT to arbitrary two-dimensional <br />
electromagnetic problems with general anisotropic material [26]. Based on a unified (E_z, H_z)<br />
formulation, the scattering problem when a plane wave is obliquely incident upon an <br />
inhomogeneous and anisotropic dielectric cylinder. The variational equation is then derived <br />
with all the exterior problem absorbed into the boundary operator and then solved by the finite <br />
element method. The scattering cross sections of radiation problems can be obtained. In <br />
addition, the guiding problems of dielectric waveguides are also solved by considering <br />
obliquely incident inhomogeneous waves.<br />
<br />
'''4. Partial Variational Principle to connect the VRT and the FVP and its applications to the <br />
analysis of discontinuities in dielectric waveguides'''<br />
<br />
This is the topic of the FEM@NTU paper in 1988 [11]. Its two further similar applications are <br />
published in 1989 [28] and 1990 [29]. <br />
<br />
'''5. Variational Conformal Mapping Techniques'''<br />
<br />
The 1986 paper of the FEM@NTU proposed such an idea in [9] for dielectric waveguide <br />
problems. Because it applied a clever idea to map the scalar potentials in the transverse plane <br />
into the complex plane. The original exterior field distribution is now in a closed region and can <br />
be solved easily by the FEM. With such a technique, problems with edge singularities like the <br />
microstrip and coplanar waveguide propagation problems can also be taken care of easily. <br />
References [30]-[33] are good examples.<br />
<br />
[1] P. Silvester and M.-S. Hsieh, "Finite-element solution of 2-dimensional exterior-field <br />
problems," Proceedings of the Institution of Electrical Engineers, vol. 118, no. 12, pp. <br />
1743 – 1747, 1971. doi: 10.1049/piee.1971.0320<br />
<br />
[2] B. H. McDonald and A. Wexler, "Finite-element solution of unbounded field problems," <br />
IEEE Transactions on Microwave Theory and Techniques, vol. 20, no. 12, pp. 841-<br />
847, Dec. 1972. doi: 10.1109/TMTT.1972.1127895.<br />
<br />
[3] K. Mei, "Unimoment method of solving antenna and scattering problems," IEEE <br />
Transactions on Antennas and Propagation, vol. 22, no. 6, pp. 760-766, Nov. 1974. <br />
doi: 10.1109/TAP.1974.1140894.<br />
<br />
[4] K. Morishita and N. Kumagai, "Unified approach to the derivation of variational <br />
expression for electromagnetic fields," IEEE Transactions on Microwave Theory and <br />
Techniques, vol. 25, no. 1, pp. 34-40, Jan. 1977. doi: 10.1109/TMTT.1977.1129027.<br />
<br />
[5] C. H. Chen and C.-D. Lien, "The variational principle for non-self-adjoint<br />
electromagnetic problems," IEEE Transactions on Microwave Theory and Techniques, <br />
vol. MTT-28, no. 8, pp. 878-886, Aug. 1980. doi: 10.1109/TMTT.1980.1130186.<br />
<br />
[6] S.-K. Jeng and C. H. Chen, "On variational electromagnetics: Theory and application,"<br />
IEEE Transactions on Antennas and Propagation, vol. AP-32, no. 9, pp. 902-907, Sept.<br />
1984. doi: 10.1109/TAP.1984.1143439<br />
<br />
[7] H.-C. Chang, S.-K. Jeng, R.-B. Wu, and C. H. Chen," Propagation of waves through <br />
magnetoplasma slab within a parallel-plate guide," IEEE Transactions on Microwave <br />
Theory and Techniques, vol. MTT-34, no. 1, pp. 50-54. Jan. 1986, doi: 10.1109/8.1074<br />
<br />
[8] C.-C. Su, "A combined method for dielectric waveguides using the finite-element <br />
technique and surface integral equations method," IEEE Transactions on Microwave <br />
Theory and Techniques, vol. MTT-34, no. 11, pp. 1140-1146, Nov. 1986. doi: 10.1109/<br />
TMTT.1986.1133511<br />
<br />
[9] R.-B. Wu and C. H. Chen, "A scalar variational conformal mapping technique for weakly <br />
guiding dielectric waveguides," IEEE Journal of Quantum Electronics, vol. QE-22, no. <br />
3, 1986, pp. 603-609. doi: 10.1109/JQE.1986.1073014<br />
<br />
[10] R.-B. Wu and C. H. Chen, "On the variational reaction theory for dielectric <br />
waveguides," IEEE Transactions on Microwave Theory and Techniques, vol. MTT-33, <br />
no. 6, pp. 477-483, June 1985. doi: 10.1109/TMTT.1985.1133102<br />
<br />
[11] S.-J. Chung and C. H. Chen, "Partial variational principle for electromagnetic field <br />
problems: Theory and applications," IEEE Transactions on Microwave Theory and <br />
Techniques, vol. MTT-36, no. 3, pp. 473-479, Mar. 1988. doi: 10.1109/22.3537<br />
<br />
[12] J.‐F. Lee and Z. J. Cendes, "Transfinite elements: A highly efficient procedure for <br />
modeling open field problems," Journal of Applied Physics 61, 3913 (1987). https:// <br />
doi.org/10.1063/1.338582<br />
The variational formulation in this paper is similar to the one in a FEM@NTU 1982 <br />
paper: S.-K. Jeng and C. H. Chen, "A new variational theory for linear field problems <br />
and its application to electrostatics," Journal of the Chinese Institute of Engineers, vol. <br />
5, no. 2, 1982, pp. 99-107. https://doi.org/10.1080/02533839.1982.9676696<br />
<br />
[13] J.-F. Lee and Z. J. Cendes, "The transfinite element method for computing <br />
electromagnetic scattering from arbitrary lossy cylinders," in 1987 International <br />
Symposium on Antennas and Propagation, pp. 99-102, Jan. 1987, doi: 10.1109/<br />
APS.1987.1150085.<br />
The variational formulation in this paper is similar to the one derived in a FEM@NTU <br />
1984 paper [6].<br />
<br />
[14] Z. J. Cendes and J.-F. Lee, "The transfinite element method for modeling MMIC <br />
devices," IEEE Transactions on Microwave Theory and Techniques, vol. 36, no. 12, <br />
pp. 1639-1649, Dec. 1988. doi: 10.1109/22.17395.<br />
,<br />
<br />
[15] J. F. Lee, D. K. Sun and Z. J. Cendes, "Tangential vector finite elements for <br />
electromagnetic field computation," IEEE Transactions on Magnetics, vol. 27, no. 5, <br />
pp. 4032-4035, Sept. 1991. doi: 10.1109/20.104986.<br />
<br />
[16] J.-M. Jin and V. V. Liepa, "Application of hybrid finite element method to <br />
electromagnetic scattering from coated cylinders," IEEE Transactions on Antennas <br />
and Propagation, vol. 36, no. 1, Jan. 1988, pp. 50-54. doi: 10.1109/8.1074<br />
<br />
[17] J.-M. Jin and V. V. Liepa, "A note on hybrid finite element method for solving scattering <br />
problems," IEEE Transactions on Antennas and Propagation, vol. 36, no. 10, pp. 1486-<br />
1490, Oct. 1988. doi: 10.1109/8.8638.<br />
<br />
[18] J.-M. Jin and J. L. Volakis, "Scattering and radiation from microstrip patch antennas <br />
and arrays residing in a cavity," in 1991 International Symposium on Antennas and <br />
Propagation, pp. 657-660 vol.2. 1991, doi: 10.1109/APS.1991.174925.<br />
<br />
[19] X.-Q. Sheng, J.-M. Jin, J. Song, C.-C. Lu, and W. C. Chew, "On the formulation of <br />
hybrid finite-element and boundary-integral methods for 3-D scattering," IEEE <br />
Transactions on Antennas and Propagation, vol. 46, no. 3, pp. 303-311, March 1998.<br />
doi: 10.1109/8.662648.<br />
<br />
[20] C. H. Chen, "Some remarks on exterior electromagnetic boundary value problems for <br />
spheres," IEEE Transactions on Antennas and Propagation, vol. 18, no. 5, pp. 705-<br />
707, Sept. 1970. doi: 10.1109/TAP.1970.1139747.<br />
<br />
[21] C. H. Chen and C.-D. Lien, "A finite element solution of the wave propagation problem <br />
for an inhomogeneous dielectric slab," IEEE Transactions on Antennas and <br />
Propagation, vol. 27, no. 6, pp. 877-880, Nov. 1979. doi: 10.1109/TAP.1979.1142199.<br />
<br />
[22] C.-H. Chen and Y.-W. Kiang, "A variational theory for wave propagation in a one-dimensional inhomogeneous medium," IEEE Transactions on Antennas and <br />
Propagation, vol. 28, no. 6, pp. 762-769, Nov. 1980. doi: 10.1109/TAP.1980.1142435.<br />
<br />
[23] C.-T. Liu and C. H. Chen, "A variational theory for wave propagation in inhomogeneous <br />
dielectric slab loaded waveguides," IEEE Transactions on Microwave Theory and <br />
Techniques, vol. 29, no. 8, pp. 805-812, Aug. 1981. doi: 10.1109/TMTT.1981.1130451.<br />
<br />
[24] S.-K. Jeng and C. H. Chen, "Variational finite element solution of electromagnetic wave <br />
propagation in a one‐dimensional inhomogeneous anisotropic medium," Journal of <br />
Applied Physics 55, 630, 1984. https://doi.org/10.1063/1.333115<br />
<br />
[25] S.-K. Jeng, R.-B. Wu and C. H. Chen, "Waves obliquely incident upon a stratified <br />
anisotropic slab: A variational reaction approach," Radio Science, vol. 21, no. 4, pp. <br />
681-688, July-Aug. 1986, doi: 10.1029/RS021i004p00681.<br />
<br />
[26] R.-B. Wu and C. H. Chen, "Variational reaction formulation of scattering problem for <br />
anisotropic dielectric cylinders," IEEE Transactions on Antennas and Propagation, vol. <br />
34, no. 5, pp. 640-645, May 1986, doi: 10.1109/TAP.1986.1143874.<br />
<br />
[27] R.-B. Wu and C. H. Chen, "Birefringence analysis of anisotropic optical fibers using <br />
variational reaction theory," IEEE Transactions on Microwave Theory and Techniques, <br />
vol. 34, no. 6, pp. 741-745, June 1986, doi: 10.1109/TMTT.1986.1133428.<br />
<br />
[28] S.-J. Chung and C. H. Chen, "A partial variational approach for arbitrary discontinuities <br />
in planar dielectric waveguides," IEEE Transactions on Microwave Theory and <br />
Techniques, vol. MTT-37, no. 1, pp. 208 - 214, Jan. 1989. doi: 10.1109/22.20040<br />
<br />
[29] S.-J. Chung and C. H. Chen, "A partial variational analysis of planar dielectric <br />
antennas," IEEE Transactions on Antennas and Propagation, vol. 39, no. 6, pp. 713 -<br />
718, Jun. 1991. doi: 10.1109/8.86867<br />
<br />
[30] C. Shih, R. -B. Wu, S.-K. Jeng, and C. H. Chen, "A full-wave analysis of microstrip <br />
lines by variational conformal mapping technique," IEEE Transactions on Microwave <br />
Theory and Techniques, vol. 36, no. 3, pp. 576-581, Mar. 1988, doi: 10.1109/22.3551.<br />
<br />
[31] C. Shih, R.-B. Wu, S.-K. Jeng, and C. H. Chen, "Frequency-dependent characteristics <br />
of open microstrip lines with finite strip thickness," IEEE Transactions on Microwave <br />
Theory and Techniques, vol. 37, no. 4, pp. 793-795, April 1989, doi: 10.1109/22.18856.<br />
<br />
[32] C. –N. Chang, Y. –C. Wong, and C. H. Chen, "Full-wave analysis of coplanar <br />
waveguides by variational conformal mapping technique," IEEE Transactions on <br />
Microwave Theory and Techniques, vol. 38, no. 9, pp. 1339 - 1344, Sep. 1990, doi: <br />
10.1109/22.58662.<br />
<br />
[33] C. –N. Chang, W. –C. Chang, and C. H. Chen, "Full-wave analysis of multilayer <br />
coplanar lines," IEEE Transactions on Microwave Theory and Techniques, vol. 39, no. <br />
4, pp. 747 - 750, April 1991, doi: 10.1109/22.76444.<br />
|submitted=No<br />
}}</div>Administrator1http://ieeemilestones.ethw.org/index.php?title=File:Varational_electromagnetics_plaque.jpg&diff=11154File:Varational electromagnetics plaque.jpg2021-06-14T14:36:19Z<p>Administrator1: </p>
<hr />
<div></div>Administrator1http://ieeemilestones.ethw.org/index.php?title=Milestone-Proposal:Theoretical_Foundation_of_Finite-Element-Method_for_Electromagnetics&diff=11153Milestone-Proposal:Theoretical Foundation of Finite-Element-Method for Electromagnetics2021-06-14T14:34:57Z<p>Administrator1: </p>
<hr />
<div>{{Proposal<br />
|litigation=No<br />
|more than 25 years=Yes<br />
|within fields of interest=Yes<br />
|benefit to humanity=Yes<br />
|regional importance=Yes<br />
|ou is paying=Yes<br />
|ou is arranging dedication=Yes<br />
|section is taking responsibility for plaque=Yes<br />
|a11=Yes<br />
|a3=1979 -1991<br />
|a1=Theoretical Foundation of Finite-Element-Method for Electromagnetics<br />
|plaque citation=From 1979 to 1991, an electromagnetic-wave research group in the department of electrical <br />
engineering, National Taiwan University, laid the theoretical foundation for the Finite Element <br />
Method for general linear Electromagnetic field problems. They also found a straightforward<br />
derivation as a generalized Galerkin's method. It has been widely applied in academic <br />
researches and commercial software development, like the early versions of HFSS.<br />
<br />
1979 至 1991 期間，台大電機系的電波研究團隊建構了應用於一般線性電磁學問題的有限元素<br />
法理論基礎。他們也發現有限元素法的矩陣方程式，可以由推廣的 Galerkin 方法直接完成。這種<br />
推廣的 Galerkin 方法很快就應用到許多學術研究以及廣為應用的商業模擬軟體開發，如 HFSS。<br />
|a2b=IEEE Taipei Section<br />
|IEEE units paying={{IEEE Organizational Unit Paying<br />
|Unit=IEEE Taipei Section<br />
|Senior officer name=Kea-Tiong Tang, Chairman<br />
}}<br />
|IEEE units arranging={{IEEE Organizational Unit Arranging<br />
|Unit=IEEE Taipei Section<br />
|Senior officer name=Kea-Tiong Tang, Chairman<br />
}}<br />
|IEEE sections monitoring={{IEEE Section Monitoring<br />
|Section=IEEE Taipei Section<br />
|Section chair name=Kea-Tiong Tang, Chairman<br />
}}<br />
|Milestone proposers={{Milestone proposer<br />
|Proposer name=Shyh-Kang Jeng, Ruey-Beei Wu, and Jin-Fa Lee<br />
|Proposer email=skjeng@ntu.edu.tw, rbwu@ntu.edu.tw, and jin.fa.lee.1863@gmail.com<br />
}}<br />
|a2a=Department of Electrical Engineering, National Taiwan University, 1, Sec. 4, Roosevelt Rd., Taipei, Taiwan 10617. GPS coordinates: x 25.01953, y 121.54410<br />
|a7=The intended site is inside the main department building, which started its construction when Professor Chun Hsiung Chen, the team leader for the proposed milestone, served as the department head from 1982 to 1985. In this building, Professor Chen and his students in the team taught and developed further applications of the milestone. However, the major works of the proposed milestone were conducted earlier in the now civil engineering building, about 600 meters away. This building now accommodates more than 2500 students, including 800 undergraduates, 1200 master, and 500 Ph.D. students, reside to study various areas in electrical engineering. It is the "powerhouse" in Taiwan to promote the innovation, education, and promotion of electrical engineering for humanity.<br />
|a8=The original buildings where the development took place now serve a different goal, are no longer publicly accessible, and will probably be demolished within a few years.<br />
|mounting details=The intended location is near the entrance of the auditorium in the building, where the seminars, conferences, and invited lectures are frequently held. A picture giving an overview of the entrance of the auditorium is shown below. The IEEE can consult the department of Electrical Engineering about the exact place and mounting within the building<br />
|a9=The building is opened on weekdays. The site is protected/secured by a management team and security cameras.<br />
|a10=Chairman Chung-Chih Wu, Department of Electrical Engineering, National Taiwan University<br />
|a4=The Finite-Element Method (FEM) has been popular in modeling linear electromagnetic fields, <br />
from radiation, scattering, waveguide, to high-frequency circuits. To get a matrix equation for <br />
FEM, we have to derive a variational equation first. The applications of finite element methods <br />
for static fields were understood, and the variational nature of the formulation was well <br />
documented. However, for electromagnetic wave radiations and scattering problems, the <br />
underlying physics is non-Hermitian, and the corresponding variational principle was lacking in <br />
the 1980s. <br />
<br />
Consequently, the work's significance is: proposing a systematic method for derivation of <br />
variational equations, including exterior fields in the variational equations, and discovering a <br />
shortcut for deriving the FEM matrix equations directly. The inclusion of exterior field results in <br />
the popularity of the hybrid element method, and the shortcut method was a generalized <br />
Galerkin's method. Such a shortcut and the hybrid finite element method have been widely <br />
used for academic research and successful commercial software development, like the early <br />
versions of HFSS software (High-Frequency Structure Simulation).<br />
|a6=The major obstacles needed to be overcome by the FEM team led by Professor Chun Hsiung <br />
Chen (FEM@NTU) are: difficulty in treating non-self-adjoint fields, unsystematic methods for <br />
the variational formulation, difficulty in dealing with exterior fields, difficulty to find physical <br />
interpretation, tedious approaches for obtaining the FEM matrix equations, and challenge to <br />
prove that the proposed shortcut method is consistent with the proposed fundamental<br />
variational equation.<br />
<br />
'''Difficulty in Treating Non-self-adjoint fields'''<br />
<br />
Before 1980, most papers about variational formulation assume that the problem as an operator <br />
equation together with boundary conditions is self-adjoint. The inner product of a field with an <br />
operator operated on another field with associated boundary conditions is the same if we switch <br />
positions of the field and the operator. This reciprocity does not hold for a non-self-adjoint <br />
problem. For an example of the non-self-adjoint problem, consider the situation with <br />
anisotropic materials whose characteristics are described by non-symmetric and/or non-Hermitian matrices. <br />
<br />
The FEM@NTU team in 1980 first proposed a general variational formulation with an adjoint <br />
problem to handle a non-self-adjoint problem. The solution of the adjoint problem is related <br />
to problems with the material characteristics being the transpose or Hermitian of those of the <br />
original problem. Although the adjoint field is introduced, we still need to solve only the field <br />
distribution of the original problem with the FEM. The 1980 paper also provided physical <br />
interpretation through a concept of generalized reaction. However, it did not reveal how to <br />
extend the formulation for general exterior problems.<br />
<br />
'''Unsystematic derivation of variational formulation'''<br />
<br />
For mechanics, a variational equation is often obtained from the least action principle. For <br />
electromagnetics, the application of the FEM for exterior field problems is scarce before 1984.<br />
The most related papers are: Silvester and Hsieh (1971) [1], McDonald and Wexler (1972) [2], <br />
the Unimoment method (Mei, 1974) [3], and Morishita and Kumagai (1977) [4]. The variational <br />
equations in these works are derived case by case after setting up systems of partial differential <br />
equations from the Maxwell equation, except for Morishita and Kumagai in 1977, in which the <br />
formulation started from the least action principle generalized for electromagnetic fields. <br />
However, their approach is inconvenient and indirect for use since the formulation involves <br />
vector and scalar potentials.<br />
The FEM@NTU team first proposed in 1980 (primarily for interior problems and simple one-dimensional problems) [5] and 1984 (with extension to general exterior problems) [6] that the <br />
FEM equations for any linear Electromagnetic field problems can be deduced from setting the <br />
Fundamental Variational Principle (FVP) to be stationary, equivalent to the Maxwell equations<br />
along with the associated boundary conditions. Variational equations can be deduced simply <br />
by applying problem-dependent constraints to reduce the FVP. <br />
<br />
'''Difficulty in Dealing with Exterior Fields'''<br />
<br />
Silvester and Hsieh [1] applied Green's theorem to obtain a variational equation by treating the <br />
outer region as a single exterior element. However, they dealt with only 2D Laplace equations, <br />
i.e., static fields only. McDonald and Wexler [2] treated an Integral equation as a constraint to <br />
replace the exterior element. Their paper also shows that they can handle only 2-D Poisson <br />
equations, again, static fields only. Mei [3] proposed the unimoment method. He imposed an <br />
artificial boundary and expressed the exterior and interior fields as sums of eigenmodes and <br />
pseudo modes, respectively. A pseudo mode for the internal problem was obtained by the FEM <br />
with enforcing boundary conditions on the artificial boundary like an exterior eigenmode. The coefficients of both series were then acquired by matching the continuity conditions on the <br />
artificial boundary. The exterior field was not included in the variational equations directly.<br />
<br />
The FEM@NTU team expressed the exterior field in the following ways: a sum of eigenmodes <br />
(including scattering wave modes [6] and propagation modes in general waveguide [7]) or an <br />
integral over the artificial interior-exterior boundary [8]. Such expressions are then included<br />
in the functional with careful treatment for keeping their stationarity. In addition, the <br />
FEM@NTU team also proposed an attractive approach for dielectric waveguide problems. For <br />
such problems, 2-D transverse trial fields extending to infinity in the stationary functional are <br />
transformed into the inside of a closed region in the complex plane by a conformal mapping<br />
[9]. The exterior fields are thus taken into considerations automatically.<br />
<br />
'''Difficulty to Find Physical interpretation'''<br />
<br />
Many early publications about variational formulation describe their results with mathematic <br />
manipulation only. The variational principles derived by the FEM@NTU team in 1980 [5] and <br />
1984 [6] were with a physical interpretation of general reaction. Note also the stationarity of <br />
the FVP is equivalent to the Maxwell equations along with the boundary conditions, just like <br />
that the principle of virtual work is equivalent to Newton's laws in statics and dynamics. Also,<br />
in the 1984 paper [6], the FVP can be reduced to a form as oscillatory power if the problem is <br />
self-adjoint, which is similar to the least action principle for mechanics.<br />
<br />
'''Tedious Approaches for Obtaining the FEM matrix equations'''<br />
<br />
The process of obtaining a FEM matrix equation from the FVP by applying problem-related <br />
constraints and the Ritz procedure are pretty tedious, though systematic. The FEM@NTU <br />
team's 1985 paper introduced the Variational Reaction Theory (VRT) [10] to derive the required <br />
matrix equation and found it a generalization of the conventional Galerkin's method. <br />
<br />
'''Difficulty in Proving the Shortcut Being Consistent with the Fundamental Variational <br />
Equation'''<br />
<br />
The stationarity of the FVP proposed in 1984 [6] is equivalent to the Maxwell equations and <br />
should hold for all linear electromagnetic field problems. The VRT [10] is more efficient in <br />
deriving the required FEM matrix equations. However, its consistency with the variational <br />
equation of FVP was not clear. In other words, why does the generalized Galerkin's method <br />
work? Why does the way to deal with the exterior field in the generalized Galerkin's method <br />
lead to the correct solution? Such essential theoretical questions were answered in a FEM@NTU <br />
paper in 1988, in which the team proposed the concept of the Partial Variational Principle (PVP) <br />
[11]. By PVP, the variation on a functional of trial field f and its adjoint f<sup>a</sup>, like the partial <br />
differentiation, equals the sum of two functionals (PVPs), where one is obtained by taking partial <br />
variation with respect to f while the other is taken with respect to f<sup>a</sup>. If only field f is to be solved, <br />
the functional by taking partial variation to f can be ignored. The resultant partial variational <br />
principle is just the same as the starting equation of VRT. The consistency of VRT and the <br />
variational equation on the FVP is thus proved.<br />
|a5=Features of this series of work are given below:<br />
#First variational formulation equivalent to the Maxwell equations and associated boundary conditions. Also proposed are their physical interpretations.<br />
#A systematic approach to derive the FEM matrix equations.<br />
#First inclusion of exterior field in the variational equation, which leads to the now popular hybrid finite element method.<br />
#First shortcut to derive the FEM matrix equations directly, which is equivalent to a generalized Galerkin's method and widely used in academic and commercial software development circles.<br />
#A conformal mapping technique for dielectric waveguide problems to transform the two-dimensional transverse field into the inside of a closed region. Solving the fields in this closed region by the FEM handles the exterior fields automatically.<br />
<br />
'''Later development'''<br />
<br />
Since the FEM@NTU team published their 1985 papers, the generalized Galerkin's method <br />
becomes very popular in solving the scattering of objects in free space and waveguide <br />
structures. The primarily related papers are those introducing the transfinite element method <br />
(Lee and Cendes, 1987, 1987 [12], [13]; Cendes and Lee, 1988 [14]; Lee, Sun, and Cendes, 1991<br />
[15]), and those emphasizing hybrid finite element methods for the scattering of objects in free <br />
space (Jin and Liepa, 1988 [16]; Jin and Liepa, 1988 [17]). The transfinite element method was <br />
then applied for developing the commercial software HFSS for dealing with RF, microwave, and <br />
millimeter-wave circuits. The hybrid finite element method has also been proved efficient and <br />
effective in solving realistic scattering problems (for example, Jin and Volakis, 1991 [18] and <br />
Shen et al., 1998 [19]). However, the impact of the generalized Galerkin's method is not limited <br />
by its applications to solving electromagnetic wave problems with the finite element methods. <br />
Professor Jin-Fa Lee at the Ohio State University also recognized the strong correlation of the <br />
generalized Galerkin's method with the reciprocity theorem in electromagnetic fields and the <br />
popular Bi-CG methods for solving complex symmetric but non-Hermitian matrices equations.<br />
<br />
'''The FEM@NTU team'''<br />
<br />
The FEM@NTU leader, Professor Chen, is the first faculty in Taiwan who published papers in <br />
IEEE journals (as early as 1970 [20]). He and his students published their first FEM paper on <br />
applying the FEM to a one-dimensional problem with inhomogeneous dielectric in free space <br />
in 1979 [21], [22] and a rectangular waveguide in 1981 [23]. Later the FEM@NTU team began <br />
to focus on finding a general variational equation for electromagnetic field problems. They <br />
published papers on the fundamental variational principles (FVP) in 1980 [5] and 1984 [6], <br />
respectively. A shortcut, the VRT, for deriving FEM matrix equations from the FVP was then <br />
proposed in their 1985 paper [10]. Finally, in 1988, the FEM@NTU team proposed the partial <br />
variational principle [11] and proved that the VRT is consistent with the variational equation on <br />
the FVP.<br />
<br />
Not restricted to pure and abstract mathematic formulation, based on the FVP, VRT, and PVP, <br />
Professor Chen and his students published various applications. The applications include: the <br />
scattering of the perfect electric conductor (PEC) cylinder with inhomogeneous dielectric <br />
coating [6], general scattering from anisotropic inhomogeneous slabs [24], [25] and cylinders<br />
[26], scattering from a magnetostatic slab in parallel-plate waveguide [7], general analysis of <br />
dielectric waveguides [8], [10], birefringence analysis of anisotropic optical fibers [27], and <br />
analysis of discontinuities in a dielectric waveguide [11] and planar dielectric waveguides [28], <br />
and planar dielectric antennas [29], For weakly guiding dielectric waveguides [9], microstrip lines<br />
[30], [31], and coplanar waveguides [32], [33], the FEM@NTU team conceived a delicate idea, <br />
the Variational Conformal Mapping technique [9], to transform the problem onto a complex <br />
plane, and wherein solve a scalar field.<br />
<br />
'''Further information'''<br />
<br />
Jin-Fa Lee is the major developer of the booming commercial software HFSS. He took <br />
Professor Chen's course on mathematical physics, which introduced variational formulation <br />
coupled with the FEM in 1981 when he was an undergraduate student in the National Taiwan <br />
University's electric engineering department. Afterward, he pursued his Ph.D. studies at<br />
Carnegie Mellon University under the supervision of Professor Zoltan J. Cendes, father of HFSS <br />
and the founder of Ansoft Corp. Note Ansoft Corp. was later acquired by Ansys Corp.<br />
|references='''1. General variational principle for interior field problems and simple one-dimensional <br />
transmission-reflection problems'''<br />
<br />
The work [5] is included as a reference in Chapter 6, Variational Principles for Electromagnetics, <br />
The Finite Element Method in Electromagnetics, by Jianming Jin, New York, USA: John Wiley & <br />
Sons, Inc., 1993, a popular textbook for learning the FEM for electromagnetics. In that chapter, <br />
Professor Jin commented on the use of variational equations as: "It is only in recent years that <br />
the variational formulation has been discussed more extensively, mainly to satisfy the need for <br />
finite element method … However, even these methods remain unknown to many researchers <br />
and generally are not taught to graduate students. This situation is in contrast to that of <br />
Galerkin's method, which is a popular choice both in research and instruction, possibly because <br />
of its simplicity."<br />
<br />
We agree that starting the FEM with a general variational formulation requires much<br />
mathematical background, and its derivation is not as straightforward as the generalized <br />
Galerkin's method. However, the FEM@NTU team also found this shortcut [10] and provided <br />
it with a more rigorous theoretical foundation [11].<br />
<br />
Jin also said: "If we indeed establish a general procedure to derive the variational formulation <br />
for any given problem, there will be no major obstacles, except for personal preference, to <br />
prevent us from employing the variational method for the finite element formulation." Here Jin <br />
skipped our general variational equation of FVP, which could be due to the abstract <br />
mathematics in the FEM@NTU work [6], especially in including the exterior field into the <br />
variational equation. Actually, in Jin's book, the functional given is derived from the <br />
generalized Galerkin's method while fine-tuning some boundary terms to ensure that the <br />
functional is stationary.<br />
<br />
Another book, Finite Elements for Wave Electromagnetics: Method and Techniques edited by <br />
Peter P. Silvester and Giuseppe Pelosi, New York, USA: IEEE Press, 1994, collected papers <br />
important to applications of the FEM to electromagnetics. The FEM@NTU contributions [5]<br />
about the general variational formulation and [25] about the VRT were included.<br />
<br />
'''2. Fundamental Variational Principle (FVP) and inclusion of exterior field as hybrid finite <br />
element method'''<br />
<br />
The FVP was proposed in 1984 [6]. It has been applied to model the scattering matrix <br />
coefficients for microwave circuit elements, such as [7]. The transfinite element method in [14] <br />
used a similar approach, though the FEM matrix equations are obtained from the generalized <br />
Galerkin's method. <br />
<br />
A similar approach with another hybrid finite element method for dielectric waveguide analysis<br />
was utilized by Su [8], also Professor Chun Hsiung Chen's student.<br />
<br />
Such a hybrid finite element method for scattering problems was a contribution of Jin [16].<br />
<br />
'''3. Variational Reaction Theory (VRT) as a generalized Glerkin's method'''<br />
<br />
As mentioned above, the VRT [10] became a popular shortcut as a generalized Galerkin's <br />
method in deriving equations for FEM. A lot of published FEM works were based on this <br />
approach. One typical example is applying the VRT to arbitrary two-dimensional <br />
electromagnetic problems with general anisotropic material [26]. Based on a unified (E_z, H_z)<br />
formulation, the scattering problem when a plane wave is obliquely incident upon an <br />
inhomogeneous and anisotropic dielectric cylinder. The variational equation is then derived <br />
with all the exterior problem absorbed into the boundary operator and then solved by the finite <br />
element method. The scattering cross sections of radiation problems can be obtained. In <br />
addition, the guiding problems of dielectric waveguides are also solved by considering <br />
obliquely incident inhomogeneous waves.<br />
<br />
'''4. Partial Variational Principle to connect the VRT and the FVP and its applications to the <br />
analysis of discontinuities in dielectric waveguides'''<br />
<br />
This is the topic of the FEM@NTU paper in 1988 [11]. Its two further similar applications are <br />
published in 1989 [28] and 1990 [29]. <br />
<br />
'''5. Variational Conformal Mapping Techniques'''<br />
<br />
The 1986 paper of the FEM@NTU proposed such an idea in [9] for dielectric waveguide <br />
problems. Because it applied a clever idea to map the scalar potentials in the transverse plane <br />
into the complex plane. The original exterior field distribution is now in a closed region and can <br />
be solved easily by the FEM. With such a technique, problems with edge singularities like the <br />
microstrip and coplanar waveguide propagation problems can also be taken care of easily. <br />
References [30]-[33] are good examples.<br />
<br />
[1] P. Silvester and M.-S. Hsieh, "Finite-element solution of 2-dimensional exterior-field <br />
problems," Proceedings of the Institution of Electrical Engineers, vol. 118, no. 12, pp. <br />
1743 – 1747, 1971. doi: 10.1049/piee.1971.0320<br />
<br />
[2] B. H. McDonald and A. Wexler, "Finite-element solution of unbounded field problems," <br />
IEEE Transactions on Microwave Theory and Techniques, vol. 20, no. 12, pp. 841-<br />
847, Dec. 1972. doi: 10.1109/TMTT.1972.1127895.<br />
<br />
[3] K. Mei, "Unimoment method of solving antenna and scattering problems," IEEE <br />
Transactions on Antennas and Propagation, vol. 22, no. 6, pp. 760-766, Nov. 1974. <br />
doi: 10.1109/TAP.1974.1140894.<br />
<br />
[4] K. Morishita and N. Kumagai, "Unified approach to the derivation of variational <br />
expression for electromagnetic fields," IEEE Transactions on Microwave Theory and <br />
Techniques, vol. 25, no. 1, pp. 34-40, Jan. 1977. doi: 10.1109/TMTT.1977.1129027.<br />
<br />
[5] C. H. Chen and C.-D. Lien, "The variational principle for non-self-adjoint<br />
electromagnetic problems," IEEE Transactions on Microwave Theory and Techniques, <br />
vol. MTT-28, no. 8, pp. 878-886, Aug. 1980. doi: 10.1109/TMTT.1980.1130186.<br />
<br />
[6] S.-K. Jeng and C. H. Chen, "On variational electromagnetics: Theory and application,"<br />
IEEE Transactions on Antennas and Propagation, vol. AP-32, no. 9, pp. 902-907, Sept.<br />
1984. doi: 10.1109/TAP.1984.1143439<br />
<br />
[7] H.-C. Chang, S.-K. Jeng, R.-B. Wu, and C. H. Chen," Propagation of waves through <br />
magnetoplasma slab within a parallel-plate guide," IEEE Transactions on Microwave <br />
Theory and Techniques, vol. MTT-34, no. 1, pp. 50-54. Jan. 1986, doi: 10.1109/8.1074<br />
<br />
[8] C.-C. Su, "A combined method for dielectric waveguides using the finite-element <br />
technique and surface integral equations method," IEEE Transactions on Microwave <br />
Theory and Techniques, vol. MTT-34, no. 11, pp. 1140-1146, Nov. 1986. doi: 10.1109/<br />
TMTT.1986.1133511<br />
<br />
[9] R.-B. Wu and C. H. Chen, "A scalar variational conformal mapping technique for weakly <br />
guiding dielectric waveguides," IEEE Journal of Quantum Electronics, vol. QE-22, no. <br />
3, 1986, pp. 603-609. doi: 10.1109/JQE.1986.1073014<br />
<br />
[10] R.-B. Wu and C. H. Chen, "On the variational reaction theory for dielectric <br />
waveguides," IEEE Transactions on Microwave Theory and Techniques, vol. MTT-33, <br />
no. 6, pp. 477-483, June 1985. doi: 10.1109/TMTT.1985.1133102<br />
<br />
[11] S.-J. Chung and C. H. Chen, "Partial variational principle for electromagnetic field <br />
problems: Theory and applications," IEEE Transactions on Microwave Theory and <br />
Techniques, vol. MTT-36, no. 3, pp. 473-479, Mar. 1988. doi: 10.1109/22.3537<br />
<br />
[12] J.‐F. Lee and Z. J. Cendes, "Transfinite elements: A highly efficient procedure for <br />
modeling open field problems," Journal of Applied Physics 61, 3913 (1987). https:// <br />
doi.org/10.1063/1.338582<br />
The variational formulation in this paper is similar to the one in a FEM@NTU 1982 <br />
paper: S.-K. Jeng and C. H. Chen, "A new variational theory for linear field problems <br />
and its application to electrostatics," Journal of the Chinese Institute of Engineers, vol. <br />
5, no. 2, 1982, pp. 99-107. https://doi.org/10.1080/02533839.1982.9676696<br />
<br />
[13] J.-F. Lee and Z. J. Cendes, "The transfinite element method for computing <br />
electromagnetic scattering from arbitrary lossy cylinders," in 1987 International <br />
Symposium on Antennas and Propagation, pp. 99-102, Jan. 1987, doi: 10.1109/<br />
APS.1987.1150085.<br />
The variational formulation in this paper is similar to the one derived in a FEM@NTU <br />
1984 paper [6].<br />
<br />
[14] Z. J. Cendes and J.-F. Lee, "The transfinite element method for modeling MMIC <br />
devices," IEEE Transactions on Microwave Theory and Techniques, vol. 36, no. 12, <br />
pp. 1639-1649, Dec. 1988. doi: 10.1109/22.17395.<br />
,<br />
<br />
[15] J. F. Lee, D. K. Sun and Z. J. Cendes, "Tangential vector finite elements for <br />
electromagnetic field computation," IEEE Transactions on Magnetics, vol. 27, no. 5, <br />
pp. 4032-4035, Sept. 1991. doi: 10.1109/20.104986.<br />
<br />
[16] J.-M. Jin and V. V. Liepa, "Application of hybrid finite element method to <br />
electromagnetic scattering from coated cylinders," IEEE Transactions on Antennas <br />
and Propagation, vol. 36, no. 1, Jan. 1988, pp. 50-54. doi: 10.1109/8.1074<br />
<br />
[17] J.-M. Jin and V. V. Liepa, "A note on hybrid finite element method for solving scattering <br />
problems," IEEE Transactions on Antennas and Propagation, vol. 36, no. 10, pp. 1486-<br />
1490, Oct. 1988. doi: 10.1109/8.8638.<br />
<br />
[18] J.-M. Jin and J. L. Volakis, "Scattering and radiation from microstrip patch antennas <br />
and arrays residing in a cavity," in 1991 International Symposium on Antennas and <br />
Propagation, pp. 657-660 vol.2. 1991, doi: 10.1109/APS.1991.174925.<br />
<br />
[19] X.-Q. Sheng, J.-M. Jin, J. Song, C.-C. Lu, and W. C. Chew, "On the formulation of <br />
hybrid finite-element and boundary-integral methods for 3-D scattering," IEEE <br />
Transactions on Antennas and Propagation, vol. 46, no. 3, pp. 303-311, March 1998.<br />
doi: 10.1109/8.662648.<br />
<br />
[20] C. H. Chen, "Some remarks on exterior electromagnetic boundary value problems for <br />
spheres," IEEE Transactions on Antennas and Propagation, vol. 18, no. 5, pp. 705-<br />
707, Sept. 1970. doi: 10.1109/TAP.1970.1139747.<br />
<br />
[21] C. H. Chen and C.-D. Lien, "A finite element solution of the wave propagation problem <br />
for an inhomogeneous dielectric slab," IEEE Transactions on Antennas and <br />
Propagation, vol. 27, no. 6, pp. 877-880, Nov. 1979. doi: 10.1109/TAP.1979.1142199.<br />
<br />
[22] C.-H. Chen and Y.-W. Kiang, "A variational theory for wave propagation in a one-dimensional inhomogeneous medium," IEEE Transactions on Antennas and <br />
Propagation, vol. 28, no. 6, pp. 762-769, Nov. 1980. doi: 10.1109/TAP.1980.1142435.<br />
<br />
[23] C.-T. Liu and C. H. Chen, "A variational theory for wave propagation in inhomogeneous <br />
dielectric slab loaded waveguides," IEEE Transactions on Microwave Theory and <br />
Techniques, vol. 29, no. 8, pp. 805-812, Aug. 1981. doi: 10.1109/TMTT.1981.1130451.<br />
<br />
[24] S.-K. Jeng and C. H. Chen, "Variational finite element solution of electromagnetic wave <br />
propagation in a one‐dimensional inhomogeneous anisotropic medium," Journal of <br />
Applied Physics 55, 630, 1984. https://doi.org/10.1063/1.333115<br />
<br />
[25] S.-K. Jeng, R.-B. Wu and C. H. Chen, "Waves obliquely incident upon a stratified <br />
anisotropic slab: A variational reaction approach," Radio Science, vol. 21, no. 4, pp. <br />
681-688, July-Aug. 1986, doi: 10.1029/RS021i004p00681.<br />
<br />
[26] R.-B. Wu and C. H. Chen, "Variational reaction formulation of scattering problem for <br />
anisotropic dielectric cylinders," IEEE Transactions on Antennas and Propagation, vol. <br />
34, no. 5, pp. 640-645, May 1986, doi: 10.1109/TAP.1986.1143874.<br />
<br />
[27] R.-B. Wu and C. H. Chen, "Birefringence analysis of anisotropic optical fibers using <br />
variational reaction theory," IEEE Transactions on Microwave Theory and Techniques, <br />
vol. 34, no. 6, pp. 741-745, June 1986, doi: 10.1109/TMTT.1986.1133428.<br />
<br />
[28] S.-J. Chung and C. H. Chen, "A partial variational approach for arbitrary discontinuities <br />
in planar dielectric waveguides," IEEE Transactions on Microwave Theory and <br />
Techniques, vol. MTT-37, no. 1, pp. 208 - 214, Jan. 1989. doi: 10.1109/22.20040<br />
<br />
[29] S.-J. Chung and C. H. Chen, "A partial variational analysis of planar dielectric <br />
antennas," IEEE Transactions on Antennas and Propagation, vol. 39, no. 6, pp. 713 -<br />
718, Jun. 1991. doi: 10.1109/8.86867<br />
<br />
[30] C. Shih, R. -B. Wu, S.-K. Jeng, and C. H. Chen, "A full-wave analysis of microstrip <br />
lines by variational conformal mapping technique," IEEE Transactions on Microwave <br />
Theory and Techniques, vol. 36, no. 3, pp. 576-581, Mar. 1988, doi: 10.1109/22.3551.<br />
<br />
[31] C. Shih, R.-B. Wu, S.-K. Jeng, and C. H. Chen, "Frequency-dependent characteristics <br />
of open microstrip lines with finite strip thickness," IEEE Transactions on Microwave <br />
Theory and Techniques, vol. 37, no. 4, pp. 793-795, April 1989, doi: 10.1109/22.18856.<br />
<br />
[32] C. –N. Chang, Y. –C. Wong, and C. H. Chen, "Full-wave analysis of coplanar <br />
waveguides by variational conformal mapping technique," IEEE Transactions on <br />
Microwave Theory and Techniques, vol. 38, no. 9, pp. 1339 - 1344, Sep. 1990, doi: <br />
10.1109/22.58662.<br />
<br />
[33] C. –N. Chang, W. –C. Chang, and C. H. Chen, "Full-wave analysis of multilayer <br />
coplanar lines," IEEE Transactions on Microwave Theory and Techniques, vol. 39, no. <br />
4, pp. 747 - 750, April 1991, doi: 10.1109/22.76444.<br />
|submitted=No<br />
}}</div>Administrator1http://ieeemilestones.ethw.org/index.php?title=Milestone-Proposal:Theoretical_Foundation_of_Finite-Element-Method_for_Electromagnetics&diff=11152Milestone-Proposal:Theoretical Foundation of Finite-Element-Method for Electromagnetics2021-06-14T14:32:57Z<p>Administrator1: </p>
<hr />
<div>{{Proposal<br />
|litigation=No<br />
|more than 25 years=Yes<br />
|within fields of interest=Yes<br />
|benefit to humanity=Yes<br />
|regional importance=Yes<br />
|ou is paying=Yes<br />
|ou is arranging dedication=Yes<br />
|section is taking responsibility for plaque=Yes<br />
|a11=Yes<br />
|a3=1979 -1991<br />
|a1=Theoretical Foundation of Finite-Element-Method for Electromagnetics<br />
|plaque citation=From 1979 to 1991, an electromagnetic-wave research group in the department of electrical <br />
engineering, National Taiwan University, laid the theoretical foundation for the Finite Element <br />
Method for general linear Electromagnetic field problems. They also found a straightforward<br />
derivation as a generalized Galerkin's method. It has been widely applied in academic <br />
researches and commercial software development, like the early versions of HFSS.<br />
<br />
1979 至 1991 期間，台大電機系的電波研究團隊建構了應用於一般線性電磁學問題的有限元素<br />
法理論基礎。他們也發現有限元素法的矩陣方程式，可以由推廣的 Galerkin 方法直接完成。這種<br />
推廣的 Galerkin 方法很快就應用到許多學術研究以及廣為應用的商業模擬軟體開發，如 HFSS。<br />
|a2b=IEEE Taipei Section<br />
|IEEE units paying={{IEEE Organizational Unit Paying<br />
|Unit=IEEE Taipei Section<br />
|Senior officer name=Kea-Tiong Tang, Chairman<br />
}}<br />
|IEEE units arranging={{IEEE Organizational Unit Arranging<br />
|Unit=IEEE Taipei Section<br />
|Senior officer name=Kea-Tiong Tang, Chairman<br />
}}<br />
|IEEE sections monitoring={{IEEE Section Monitoring<br />
|Section=IEEE Taipei Section<br />
|Section chair name=Kea-Tiong Tang, Chairman<br />
}}<br />
|Milestone proposers={{Milestone proposer<br />
|Proposer name=Shyh-Kang Jeng, Ruey-Beei Wu, and Jin-Fa Lee<br />
|Proposer email=skjeng@ntu.edu.tw, rbwu@ntu.edu.tw, and jin.fa.lee.1863@gmail.com<br />
}}<br />
|a2a=Department of Electrical Engineering, National Taiwan University, 1, Sec. 4, Roosevelt Rd., Taipei, Taiwan 10617. GPS coordinates: x 25.01953, y 121.54410<br />
|a7=The intended site is inside the main department building, which started its construction when Professor Chun Hsiung Chen, the team leader for the proposed milestone, served as the department head from 1982 to 1985. In this building, Professor Chen and his students in the team taught and developed further applications of the milestone. However, the major works of the proposed milestone were conducted earlier in the now civil engineering building, about 600 meters away. This building now accommodates more than 2500 students, including 800 undergraduates, 1200 master, and 500 Ph.D. students, reside to study various areas in electrical engineering. It is the "powerhouse" in Taiwan to promote the innovation, education, and promotion of electrical engineering for humanity.<br />
|a8=The original buildings where the development took place now serve a different goal, are no longer publicly accessible, and will probably be demolished within a few years.<br />
|mounting details=The intended location is near the entrance of the auditorium in the building, where the seminars, conferences, and invited lectures are frequently held. A picture giving an overview of the entrance of the auditorium is shown below. The IEEE can consult the department of Electrical Engineering about the exact place and mounting within the building<br />
|a9=The building is opened on weekdays. The site is protected/secured by a management team and security cameras.<br />
|a10=Chairman Chung-Chih Wu, Department of Electrical Engineering, National Taiwan University<br />
|a4=The Finite-Element Method (FEM) has been popular in modeling linear electromagnetic fields, <br />
from radiation, scattering, waveguide, to high-frequency circuits. To get a matrix equation for <br />
FEM, we have to derive a variational equation first. The applications of finite element methods <br />
for static fields were understood, and the variational nature of the formulation was well <br />
documented. However, for electromagnetic wave radiations and scattering problems, the <br />
underlying physics is non-Hermitian, and the corresponding variational principle was lacking in <br />
the 1980s. <br />
<br />
Consequently, the work's significance is: proposing a systematic method for derivation of <br />
variational equations, including exterior fields in the variational equations, and discovering a <br />
shortcut for deriving the FEM matrix equations directly. The inclusion of exterior field results in <br />
the popularity of the hybrid element method, and the shortcut method was a generalized <br />
Galerkin's method. Such a shortcut and the hybrid finite element method have been widely <br />
used for academic research and successful commercial software development, like the early <br />
versions of HFSS software (High-Frequency Structure Simulation).<br />
|a6=The major obstacles needed to be overcome by the FEM team led by Professor Chun Hsiung <br />
Chen (FEM@NTU) are: difficulty in treating non-self-adjoint fields, unsystematic methods for <br />
the variational formulation, difficulty in dealing with exterior fields, difficulty to find physical <br />
interpretation, tedious approaches for obtaining the FEM matrix equations, and challenge to <br />
prove that the proposed shortcut method is consistent with the proposed fundamental<br />
variational equation.<br />
<br />
'''Difficulty in Treating Non-self-adjoint fields'''<br />
<br />
Before 1980, most papers about variational formulation assume that the problem as an operator <br />
equation together with boundary conditions is self-adjoint. The inner product of a field with an <br />
operator operated on another field with associated boundary conditions is the same if we switch <br />
positions of the field and the operator. This reciprocity does not hold for a non-self-adjoint <br />
problem. For an example of the non-self-adjoint problem, consider the situation with <br />
anisotropic materials whose characteristics are described by non-symmetric and/or non�Hermitian matrices. <br />
<br />
The FEM@NTU team in 1980 first proposed a general variational formulation with an adjoint <br />
problem to handle a non-self-adjoint problem. The solution of the adjoint problem is related <br />
to problems with the material characteristics being the transpose or Hermitian of those of the <br />
original problem. Although the adjoint field is introduced, we still need to solve only the field <br />
distribution of the original problem with the FEM. The 1980 paper also provided physical <br />
interpretation through a concept of generalized reaction. However, it did not reveal how to <br />
extend the formulation for general exterior problems.<br />
<br />
'''Unsystematic derivation of variational formulation'''<br />
<br />
For mechanics, a variational equation is often obtained from the least action principle. For <br />
electromagnetics, the application of the FEM for exterior field problems is scarce before 1984.<br />
The most related papers are: Silvester and Hsieh (1971) [1], McDonald and Wexler (1972) [2], <br />
the Unimoment method (Mei, 1974) [3], and Morishita and Kumagai (1977) [4]. The variational <br />
equations in these works are derived case by case after setting up systems of partial differential <br />
equations from the Maxwell equation, except for Morishita and Kumagai in 1977, in which the <br />
formulation started from the least action principle generalized for electromagnetic fields. <br />
However, their approach is inconvenient and indirect for use since the formulation involves <br />
vector and scalar potentials.<br />
The FEM@NTU team first proposed in 1980 (primarily for interior problems and simple one�dimensional problems) [5] and 1984 (with extension to general exterior problems) [6] that the <br />
FEM equations for any linear Electromagnetic field problems can be deduced from setting the <br />
Fundamental Variational Principle (FVP) to be stationary, equivalent to the Maxwell equations<br />
along with the associated boundary conditions. Variational equations can be deduced simply <br />
by applying problem-dependent constraints to reduce the FVP. <br />
<br />
'''Difficulty in Dealing with Exterior Fields'''<br />
<br />
Silvester and Hsieh [1] applied Green's theorem to obtain a variational equation by treating the <br />
outer region as a single exterior element. However, they dealt with only 2D Laplace equations, <br />
i.e., static fields only. McDonald and Wexler [2] treated an Integral equation as a constraint to <br />
replace the exterior element. Their paper also shows that they can handle only 2-D Poisson <br />
equations, again, static fields only. Mei [3] proposed the unimoment method. He imposed an <br />
artificial boundary and expressed the exterior and interior fields as sums of eigenmodes and <br />
pseudo modes, respectively. A pseudo mode for the internal problem was obtained by the FEM <br />
with enforcing boundary conditions on the artificial boundary like an exterior eigenmode. The coefficients of both series were then acquired by matching the continuity conditions on the <br />
artificial boundary. The exterior field was not included in the variational equations directly.<br />
<br />
The FEM@NTU team expressed the exterior field in the following ways: a sum of eigenmodes <br />
(including scattering wave modes [6] and propagation modes in general waveguide [7]) or an <br />
integral over the artificial interior-exterior boundary [8]. Such expressions are then included<br />
in the functional with careful treatment for keeping their stationarity. In addition, the <br />
FEM@NTU team also proposed an attractive approach for dielectric waveguide problems. For <br />
such problems, 2-D transverse trial fields extending to infinity in the stationary functional are <br />
transformed into the inside of a closed region in the complex plane by a conformal mapping<br />
[9]. The exterior fields are thus taken into considerations automatically.<br />
<br />
'''Difficulty to Find Physical interpretation'''<br />
<br />
Many early publications about variational formulation describe their results with mathematic <br />
manipulation only. The variational principles derived by the FEM@NTU team in 1980 [5] and <br />
1984 [6] were with a physical interpretation of general reaction. Note also the stationarity of <br />
the FVP is equivalent to the Maxwell equations along with the boundary conditions, just like <br />
that the principle of virtual work is equivalent to Newton's laws in statics and dynamics. Also,<br />
in the 1984 paper [6], the FVP can be reduced to a form as oscillatory power if the problem is <br />
self-adjoint, which is similar to the least action principle for mechanics.<br />
<br />
'''Tedious Approaches for Obtaining the FEM matrix equations'''<br />
<br />
The process of obtaining a FEM matrix equation from the FVP by applying problem-related <br />
constraints and the Ritz procedure are pretty tedious, though systematic. The FEM@NTU <br />
team's 1985 paper introduced the Variational Reaction Theory (VRT) [10] to derive the required <br />
matrix equation and found it a generalization of the conventional Galerkin's method. <br />
<br />
'''Difficulty in Proving the Shortcut Being Consistent with the Fundamental Variational <br />
Equation'''<br />
<br />
The stationarity of the FVP proposed in 1984 [6] is equivalent to the Maxwell equations and <br />
should hold for all linear electromagnetic field problems. The VRT [10] is more efficient in <br />
deriving the required FEM matrix equations. However, its consistency with the variational <br />
equation of FVP was not clear. In other words, why does the generalized Galerkin's method <br />
work? Why does the way to deal with the exterior field in the generalized Galerkin's method <br />
lead to the correct solution? Such essential theoretical questions were answered in a FEM@NTU <br />
paper in 1988, in which the team proposed the concept of the Partial Variational Principle (PVP) <br />
[11]. By PVP, the variation on a functional of trial field f and its adjoint f<sup>a</sup>, like the partial <br />
differentiation, equals the sum of two functionals (PVPs), where one is obtained by taking partial <br />
variation with respect to f while the other is taken with respect to f<sup>a</sup>. If only field f is to be solved, <br />
the functional by taking partial variation to f can be ignored. The resultant partial variational <br />
principle is just the same as the starting equation of VRT. The consistency of VRT and the <br />
variational equation on the FVP is thus proved.<br />
|a5=Features of this series of work are given below:<br />
#First variational formulation equivalent to the Maxwell equations and associated boundary conditions. Also proposed are their physical interpretations.<br />
#A systematic approach to derive the FEM matrix equations.<br />
#First inclusion of exterior field in the variational equation, which leads to the now popular hybrid finite element method.<br />
#First shortcut to derive the FEM matrix equations directly, which is equivalent to a generalized Galerkin's method and widely used in academic and commercial software development circles.<br />
#A conformal mapping technique for dielectric waveguide problems to transform the two-dimensional transverse field into the inside of a closed region. Solving the fields in this closed region by the FEM handles the exterior fields automatically.<br />
<br />
'''Later development'''<br />
<br />
Since the FEM@NTU team published their 1985 papers, the generalized Galerkin's method <br />
becomes very popular in solving the scattering of objects in free space and waveguide <br />
structures. The primarily related papers are those introducing the transfinite element method <br />
(Lee and Cendes, 1987, 1987 [12], [13]; Cendes and Lee, 1988 [14]; Lee, Sun, and Cendes, 1991<br />
[15]), and those emphasizing hybrid finite element methods for the scattering of objects in free <br />
space (Jin and Liepa, 1988 [16]; Jin and Liepa, 1988 [17]). The transfinite element method was <br />
then applied for developing the commercial software HFSS for dealing with RF, microwave, and <br />
millimeter-wave circuits. The hybrid finite element method has also been proved efficient and <br />
effective in solving realistic scattering problems (for example, Jin and Volakis, 1991 [18] and <br />
Shen et al., 1998 [19]). However, the impact of the generalized Galerkin's method is not limited <br />
by its applications to solving electromagnetic wave problems with the finite element methods. <br />
Professor Jin-Fa Lee at the Ohio State University also recognized the strong correlation of the <br />
generalized Galerkin's method with the reciprocity theorem in electromagnetic fields and the <br />
popular Bi-CG methods for solving complex symmetric but non-Hermitian matrices equations.<br />
<br />
'''The FEM@NTU team'''<br />
<br />
The FEM@NTU leader, Professor Chen, is the first faculty in Taiwan who published papers in <br />
IEEE journals (as early as 1970 [20]). He and his students published their first FEM paper on <br />
applying the FEM to a one-dimensional problem with inhomogeneous dielectric in free space <br />
in 1979 [21], [22] and a rectangular waveguide in 1981 [23]. Later the FEM@NTU team began <br />
to focus on finding a general variational equation for electromagnetic field problems. They <br />
published papers on the fundamental variational principles (FVP) in 1980 [5] and 1984 [6], <br />
respectively. A shortcut, the VRT, for deriving FEM matrix equations from the FVP was then <br />
proposed in their 1985 paper [10]. Finally, in 1988, the FEM@NTU team proposed the partial <br />
variational principle [11] and proved that the VRT is consistent with the variational equation on <br />
the FVP.<br />
<br />
Not restricted to pure and abstract mathematic formulation, based on the FVP, VRT, and PVP, <br />
Professor Chen and his students published various applications. The applications include: the <br />
scattering of the perfect electric conductor (PEC) cylinder with inhomogeneous dielectric <br />
coating [6], general scattering from anisotropic inhomogeneous slabs [24], [25] and cylinders<br />
[26], scattering from a magnetostatic slab in parallel-plate waveguide [7], general analysis of <br />
dielectric waveguides [8], [10], birefringence analysis of anisotropic optical fibers [27], and <br />
analysis of discontinuities in a dielectric waveguide [11] and planar dielectric waveguides [28], <br />
and planar dielectric antennas [29], For weakly guiding dielectric waveguides [9], microstrip lines<br />
[30], [31], and coplanar waveguides [32], [33], the FEM@NTU team conceived a delicate idea, <br />
the Variational Conformal Mapping technique [9], to transform the problem onto a complex <br />
plane, and wherein solve a scalar field.<br />
<br />
'''Further information'''<br />
<br />
Jin-Fa Lee is the major developer of the booming commercial software HFSS. He took <br />
Professor Chen's course on mathematical physics, which introduced variational formulation <br />
coupled with the FEM in 1981 when he was an undergraduate student in the National Taiwan <br />
University's electric engineering department. Afterward, he pursued his Ph.D. studies at<br />
Carnegie Mellon University under the supervision of Professor Zoltan J. Cendes, father of HFSS <br />
and the founder of Ansoft Corp. Note Ansoft Corp. was later acquired by Ansys Corp.<br />
|references='''1. General variational principle for interior field problems and simple one-dimensional <br />
transmission-reflection problems'''<br />
<br />
The work [5] is included as a reference in Chapter 6, Variational Principles for Electromagnetics, <br />
The Finite Element Method in Electromagnetics, by Jianming Jin, New York, USA: John Wiley & <br />
Sons, Inc., 1993, a popular textbook for learning the FEM for electromagnetics. In that chapter, <br />
Professor Jin commented on the use of variational equations as: "It is only in recent years that <br />
the variational formulation has been discussed more extensively, mainly to satisfy the need for <br />
finite element method … However, even these methods remain unknown to many researchers <br />
and generally are not taught to graduate students. This situation is in contrast to that of <br />
Galerkin's method, which is a popular choice both in research and instruction, possibly because <br />
of its simplicity."<br />
<br />
We agree that starting the FEM with a general variational formulation requires much<br />
mathematical background, and its derivation is not as straightforward as the generalized <br />
Galerkin's method. However, the FEM@NTU team also found this shortcut [10] and provided <br />
it with a more rigorous theoretical foundation [11].<br />
<br />
Jin also said: "If we indeed establish a general procedure to derive the variational formulation <br />
for any given problem, there will be no major obstacles, except for personal preference, to <br />
prevent us from employing the variational method for the finite element formulation." Here Jin <br />
skipped our general variational equation of FVP, which could be due to the abstract <br />
mathematics in the FEM@NTU work [6], especially in including the exterior field into the <br />
variational equation. Actually, in Jin's book, the functional given is derived from the <br />
generalized Galerkin's method while fine-tuning some boundary terms to ensure that the <br />
functional is stationary.<br />
<br />
Another book, Finite Elements for Wave Electromagnetics: Method and Techniques edited by <br />
Peter P. Silvester and Giuseppe Pelosi, New York, USA: IEEE Press, 1994, collected papers <br />
important to applications of the FEM to electromagnetics. The FEM@NTU contributions [5]<br />
about the general variational formulation and [25] about the VRT were included.<br />
<br />
'''2. Fundamental Variational Principle (FVP) and inclusion of exterior field as hybrid finite <br />
element method'''<br />
<br />
The FVP was proposed in 1984 [6]. It has been applied to model the scattering matrix <br />
coefficients for microwave circuit elements, such as [7]. The transfinite element method in [14] <br />
used a similar approach, though the FEM matrix equations are obtained from the generalized <br />
Galerkin's method. <br />
<br />
A similar approach with another hybrid finite element method for dielectric waveguide analysis<br />
was utilized by Su [8], also Professor Chun Hsiung Chen's student.<br />
<br />
Such a hybrid finite element method for scattering problems was a contribution of Jin [16].<br />
<br />
'''3. Variational Reaction Theory (VRT) as a generalized Glerkin's method'''<br />
<br />
As mentioned above, the VRT [10] became a popular shortcut as a generalized Galerkin's <br />
method in deriving equations for FEM. A lot of published FEM works were based on this <br />
approach. One typical example is applying the VRT to arbitrary two-dimensional <br />
electromagnetic problems with general anisotropic material [26]. Based on a unified (E_z, H_z)<br />
formulation, the scattering problem when a plane wave is obliquely incident upon an <br />
inhomogeneous and anisotropic dielectric cylinder. The variational equation is then derived <br />
with all the exterior problem absorbed into the boundary operator and then solved by the finite <br />
element method. The scattering cross sections of radiation problems can be obtained. In <br />
addition, the guiding problems of dielectric waveguides are also solved by considering <br />
obliquely incident inhomogeneous waves.<br />
<br />
'''4. Partial Variational Principle to connect the VRT and the FVP and its applications to the <br />
analysis of discontinuities in dielectric waveguides'''<br />
<br />
This is the topic of the FEM@NTU paper in 1988 [11]. Its two further similar applications are <br />
published in 1989 [28] and 1990 [29]. <br />
<br />
'''5. Variational Conformal Mapping Techniques'''<br />
<br />
The 1986 paper of the FEM@NTU proposed such an idea in [9] for dielectric waveguide <br />
problems. Because it applied a clever idea to map the scalar potentials in the transverse plane <br />
into the complex plane. The original exterior field distribution is now in a closed region and can <br />
be solved easily by the FEM. With such a technique, problems with edge singularities like the <br />
microstrip and coplanar waveguide propagation problems can also be taken care of easily. <br />
References [30]-[33] are good examples.<br />
<br />
[1] P. Silvester and M.-S. Hsieh, "Finite-element solution of 2-dimensional exterior-field <br />
problems," Proceedings of the Institution of Electrical Engineers, vol. 118, no. 12, pp. <br />
1743 – 1747, 1971. doi: 10.1049/piee.1971.0320<br />
<br />
[2] B. H. McDonald and A. Wexler, "Finite-element solution of unbounded field problems," <br />
IEEE Transactions on Microwave Theory and Techniques, vol. 20, no. 12, pp. 841-<br />
847, Dec. 1972. doi: 10.1109/TMTT.1972.1127895.<br />
<br />
[3] K. Mei, "Unimoment method of solving antenna and scattering problems," IEEE <br />
Transactions on Antennas and Propagation, vol. 22, no. 6, pp. 760-766, Nov. 1974. <br />
doi: 10.1109/TAP.1974.1140894.<br />
<br />
[4] K. Morishita and N. Kumagai, "Unified approach to the derivation of variational <br />
expression for electromagnetic fields," IEEE Transactions on Microwave Theory and <br />
Techniques, vol. 25, no. 1, pp. 34-40, Jan. 1977. doi: 10.1109/TMTT.1977.1129027.<br />
<br />
[5] C. H. Chen and C.-D. Lien, "The variational principle for non-self-adjoint<br />
electromagnetic problems," IEEE Transactions on Microwave Theory and Techniques, <br />
vol. MTT-28, no. 8, pp. 878-886, Aug. 1980. doi: 10.1109/TMTT.1980.1130186.<br />
<br />
[6] S.-K. Jeng and C. H. Chen, "On variational electromagnetics: Theory and application,"<br />
IEEE Transactions on Antennas and Propagation, vol. AP-32, no. 9, pp. 902-907, Sept.<br />
1984. doi: 10.1109/TAP.1984.1143439<br />
<br />
[7] H.-C. Chang, S.-K. Jeng, R.-B. Wu, and C. H. Chen," Propagation of waves through <br />
magnetoplasma slab within a parallel-plate guide," IEEE Transactions on Microwave <br />
Theory and Techniques, vol. MTT-34, no. 1, pp. 50-54. Jan. 1986, doi: 10.1109/8.1074<br />
<br />
[8] C.-C. Su, "A combined method for dielectric waveguides using the finite-element <br />
technique and surface integral equations method," IEEE Transactions on Microwave <br />
Theory and Techniques, vol. MTT-34, no. 11, pp. 1140-1146, Nov. 1986. doi: 10.1109/<br />
TMTT.1986.1133511<br />
<br />
[9] R.-B. Wu and C. H. Chen, "A scalar variational conformal mapping technique for weakly <br />
guiding dielectric waveguides," IEEE Journal of Quantum Electronics, vol. QE-22, no. <br />
3, 1986, pp. 603-609. doi: 10.1109/JQE.1986.1073014<br />
<br />
[10] R.-B. Wu and C. H. Chen, "On the variational reaction theory for dielectric <br />
waveguides," IEEE Transactions on Microwave Theory and Techniques, vol. MTT-33, <br />
no. 6, pp. 477-483, June 1985. doi: 10.1109/TMTT.1985.1133102<br />
<br />
[11] S.-J. Chung and C. H. Chen, "Partial variational principle for electromagnetic field <br />
problems: Theory and applications," IEEE Transactions on Microwave Theory and <br />
Techniques, vol. MTT-36, no. 3, pp. 473-479, Mar. 1988. doi: 10.1109/22.3537<br />
<br />
[12] J.‐F. Lee and Z. J. Cendes, "Transfinite elements: A highly efficient procedure for <br />
modeling open field problems," Journal of Applied Physics 61, 3913 (1987). https:// <br />
doi.org/10.1063/1.338582<br />
The variational formulation in this paper is similar to the one in a FEM@NTU 1982 <br />
paper: S.-K. Jeng and C. H. Chen, "A new variational theory for linear field problems <br />
and its application to electrostatics," Journal of the Chinese Institute of Engineers, vol. <br />
5, no. 2, 1982, pp. 99-107. https://doi.org/10.1080/02533839.1982.9676696<br />
<br />
[13] J.-F. Lee and Z. J. Cendes, "The transfinite element method for computing <br />
electromagnetic scattering from arbitrary lossy cylinders," in 1987 International <br />
Symposium on Antennas and Propagation, pp. 99-102, Jan. 1987, doi: 10.1109/<br />
APS.1987.1150085.<br />
The variational formulation in this paper is similar to the one derived in a FEM@NTU <br />
1984 paper [6].<br />
<br />
[14] Z. J. Cendes and J.-F. Lee, "The transfinite element method for modeling MMIC <br />
devices," IEEE Transactions on Microwave Theory and Techniques, vol. 36, no. 12, <br />
pp. 1639-1649, Dec. 1988. doi: 10.1109/22.17395.<br />
,<br />
<br />
[15] J. F. Lee, D. K. Sun and Z. J. Cendes, "Tangential vector finite elements for <br />
electromagnetic field computation," IEEE Transactions on Magnetics, vol. 27, no. 5, <br />
pp. 4032-4035, Sept. 1991. doi: 10.1109/20.104986.<br />
<br />
[16] J.-M. Jin and V. V. Liepa, "Application of hybrid finite element method to <br />
electromagnetic scattering from coated cylinders," IEEE Transactions on Antennas <br />
and Propagation, vol. 36, no. 1, Jan. 1988, pp. 50-54. doi: 10.1109/8.1074<br />
<br />
[17] J.-M. Jin and V. V. Liepa, "A note on hybrid finite element method for solving scattering <br />
problems," IEEE Transactions on Antennas and Propagation, vol. 36, no. 10, pp. 1486-<br />
1490, Oct. 1988. doi: 10.1109/8.8638.<br />
<br />
[18] J.-M. Jin and J. L. Volakis, "Scattering and radiation from microstrip patch antennas <br />
and arrays residing in a cavity," in 1991 International Symposium on Antennas and <br />
Propagation, pp. 657-660 vol.2. 1991, doi: 10.1109/APS.1991.174925.<br />
<br />
[19] X.-Q. Sheng, J.-M. Jin, J. Song, C.-C. Lu, and W. C. Chew, "On the formulation of <br />
hybrid finite-element and boundary-integral methods for 3-D scattering," IEEE <br />
Transactions on Antennas and Propagation, vol. 46, no. 3, pp. 303-311, March 1998.<br />
doi: 10.1109/8.662648.<br />
<br />
[20] C. H. Chen, "Some remarks on exterior electromagnetic boundary value problems for <br />
spheres," IEEE Transactions on Antennas and Propagation, vol. 18, no. 5, pp. 705-<br />
707, Sept. 1970. doi: 10.1109/TAP.1970.1139747.<br />
<br />
[21] C. H. Chen and C.-D. Lien, "A finite element solution of the wave propagation problem <br />
for an inhomogeneous dielectric slab," IEEE Transactions on Antennas and <br />
Propagation, vol. 27, no. 6, pp. 877-880, Nov. 1979. doi: 10.1109/TAP.1979.1142199.<br />
<br />
[22] C.-H. Chen and Y.-W. Kiang, "A variational theory for wave propagation in a one�dimensional inhomogeneous medium," IEEE Transactions on Antennas and <br />
Propagation, vol. 28, no. 6, pp. 762-769, Nov. 1980. doi: 10.1109/TAP.1980.1142435.<br />
<br />
[23] C.-T. Liu and C. H. Chen, "A variational theory for wave propagation in inhomogeneous <br />
dielectric slab loaded waveguides," IEEE Transactions on Microwave Theory and <br />
Techniques, vol. 29, no. 8, pp. 805-812, Aug. 1981. doi: 10.1109/TMTT.1981.1130451.<br />
<br />
[24] S.-K. Jeng and C. H. Chen, "Variational finite element solution of electromagnetic wave <br />
propagation in a one‐dimensional inhomogeneous anisotropic medium," Journal of <br />
Applied Physics 55, 630, 1984. https://doi.org/10.1063/1.333115<br />
<br />
[25] S.-K. Jeng, R.-B. Wu and C. H. Chen, "Waves obliquely incident upon a stratified <br />
anisotropic slab: A variational reaction approach," Radio Science, vol. 21, no. 4, pp. <br />
681-688, July-Aug. 1986, doi: 10.1029/RS021i004p00681.<br />
<br />
[26] R.-B. Wu and C. H. Chen, "Variational reaction formulation of scattering problem for <br />
anisotropic dielectric cylinders," IEEE Transactions on Antennas and Propagation, vol. <br />
34, no. 5, pp. 640-645, May 1986, doi: 10.1109/TAP.1986.1143874.<br />
<br />
[27] R.-B. Wu and C. H. Chen, "Birefringence analysis of anisotropic optical fibers using <br />
variational reaction theory," IEEE Transactions on Microwave Theory and Techniques, <br />
vol. 34, no. 6, pp. 741-745, June 1986, doi: 10.1109/TMTT.1986.1133428.<br />
<br />
[28] S.-J. Chung and C. H. Chen, "A partial variational approach for arbitrary discontinuities <br />
in planar dielectric waveguides," IEEE Transactions on Microwave Theory and <br />
Techniques, vol. MTT-37, no. 1, pp. 208 - 214, Jan. 1989. doi: 10.1109/22.20040<br />
<br />
[29] S.-J. Chung and C. H. Chen, "A partial variational analysis of planar dielectric <br />
antennas," IEEE Transactions on Antennas and Propagation, vol. 39, no. 6, pp. 713 -<br />
718, Jun. 1991. doi: 10.1109/8.86867<br />
<br />
[30] C. Shih, R. -B. Wu, S.-K. Jeng, and C. H. Chen, "A full-wave analysis of microstrip <br />
lines by variational conformal mapping technique," IEEE Transactions on Microwave <br />
Theory and Techniques, vol. 36, no. 3, pp. 576-581, Mar. 1988, doi: 10.1109/22.3551.<br />
<br />
[31] C. Shih, R.-B. Wu, S.-K. Jeng, and C. H. Chen, "Frequency-dependent characteristics <br />
of open microstrip lines with finite strip thickness," IEEE Transactions on Microwave <br />
Theory and Techniques, vol. 37, no. 4, pp. 793-795, April 1989, doi: 10.1109/22.18856.<br />
<br />
[32] C. –N. Chang, Y. –C. Wong, and C. H. Chen, "Full-wave analysis of coplanar <br />
waveguides by variational conformal mapping technique," IEEE Transactions on <br />
Microwave Theory and Techniques, vol. 38, no. 9, pp. 1339 - 1344, Sep. 1990, doi: <br />
10.1109/22.58662.<br />
<br />
[33] C. –N. Chang, W. –C. Chang, and C. H. Chen, "Full-wave analysis of multilayer <br />
coplanar lines," IEEE Transactions on Microwave Theory and Techniques, vol. 39, no. <br />
4, pp. 747 - 750, April 1991, doi: 10.1109/22.76444.<br />
|submitted=No<br />
}}</div>Administrator1http://ieeemilestones.ethw.org/index.php?title=Milestone-Proposal:Theoretical_Foundation_of_Finite-Element-Method_for_Electromagnetics&diff=11151Milestone-Proposal:Theoretical Foundation of Finite-Element-Method for Electromagnetics2021-06-14T14:29:25Z<p>Administrator1: </p>
<hr />
<div>{{Proposal<br />
|litigation=No<br />
|more than 25 years=Yes<br />
|within fields of interest=Yes<br />
|benefit to humanity=Yes<br />
|regional importance=Yes<br />
|ou is paying=Yes<br />
|ou is arranging dedication=Yes<br />
|section is taking responsibility for plaque=Yes<br />
|a11=Yes<br />
|a3=1979 -1991<br />
|a1=Theoretical Foundation of Finite-Element-Method for Electromagnetics<br />
|plaque citation=From 1979 to 1991, an electromagnetic-wave research group in the department of electrical <br />
engineering, National Taiwan University, laid the theoretical foundation for the Finite Element <br />
Method for general linear Electromagnetic field problems. They also found a straightforward<br />
derivation as a generalized Galerkin's method. It has been widely applied in academic <br />
researches and commercial software development, like the early versions of HFSS.<br />
<br />
1979 至 1991 期間，台大電機系的電波研究團隊建構了應用於一般線性電磁學問題的有限元素<br />
法理論基礎。他們也發現有限元素法的矩陣方程式，可以由推廣的 Galerkin 方法直接完成。這種<br />
推廣的 Galerkin 方法很快就應用到許多學術研究以及廣為應用的商業模擬軟體開發，如 HFSS。<br />
|a2b=IEEE Taipei Section<br />
|IEEE units paying={{IEEE Organizational Unit Paying<br />
|Unit=IEEE Taipei Section<br />
|Senior officer name=Kea-Tiong Tang, Chairman<br />
}}<br />
|IEEE units arranging={{IEEE Organizational Unit Arranging<br />
|Unit=IEEE Taipei Section<br />
|Senior officer name=Kea-Tiong Tang, Chairman<br />
}}<br />
|IEEE sections monitoring={{IEEE Section Monitoring<br />
|Section=IEEE Taipei Section<br />
|Section chair name=Kea-Tiong Tang, Chairman<br />
}}<br />
|Milestone proposers={{Milestone proposer<br />
|Proposer name=Shyh-Kang Jeng, Ruey-Beei Wu, and Jin-Fa Lee<br />
|Proposer email=skjeng@ntu.edu.tw, rbwu@ntu.edu.tw, and jin.fa.lee.1863@gmail.com<br />
}}<br />
|a2a=Department of Electrical Engineering, National Taiwan University, 1, Sec. 4, Roosevelt Rd., Taipei, Taiwan 10617. GPS coordinates: x 25.01953, y 121.54410<br />
|a7=The intended site is inside the main department building, which started its construction when Professor Chun Hsiung Chen, the team leader for the proposed milestone, served as the department head from 1982 to 1985. In this building, Professor Chen and his students in the team taught and developed further applications of the milestone. However, the major works of the proposed milestone were conducted earlier in the now civil engineering building, about 600 meters away. This building now accommodates more than 2500 students, including 800 undergraduates, 1200 master, and 500 Ph.D. students, reside to study various areas in electrical engineering. It is the "powerhouse" in Taiwan to promote the innovation, education, and promotion of electrical engineering for humanity.<br />
|a8=The original buildings where the development took place now serve a different goal, are no longer publicly accessible, and will probably be demolished within a few years.<br />
|mounting details=The intended location is near the entrance of the auditorium in the building, where the seminars, conferences, and invited lectures are frequently held. A picture giving an overview of the entrance of the auditorium is shown below. The IEEE can consult the department of Electrical Engineering about the exact place and mounting within the building<br />
|a9=The building is opened on weekdays. The site is protected/secured by a management team and security cameras.<br />
|a10=Chairman Chung-Chih Wu, Department of Electrical Engineering, National Taiwan University<br />
|a4=The Finite-Element Method (FEM) has been popular in modeling linear electromagnetic fields, <br />
from radiation, scattering, waveguide, to high-frequency circuits. To get a matrix equation for <br />
FEM, we have to derive a variational equation first. The applications of finite element methods <br />
for static fields were understood, and the variational nature of the formulation was well <br />
documented. However, for electromagnetic wave radiations and scattering problems, the <br />
underlying physics is non-Hermitian, and the corresponding variational principle was lacking in <br />
the 1980s. <br />
<br />
Consequently, the work's significance is: proposing a systematic method for derivation of <br />
variational equations, including exterior fields in the variational equations, and discovering a <br />
shortcut for deriving the FEM matrix equations directly. The inclusion of exterior field results in <br />
the popularity of the hybrid element method, and the shortcut method was a generalized <br />
Galerkin's method. Such a shortcut and the hybrid finite element method have been widely <br />
used for academic research and successful commercial software development, like the early <br />
versions of HFSS software (High-Frequency Structure Simulation).<br />
|a6=The major obstacles needed to be overcome by the FEM team led by Professor Chun Hsiung <br />
Chen (FEM@NTU) are: difficulty in treating non-self-adjoint fields, unsystematic methods for <br />
the variational formulation, difficulty in dealing with exterior fields, difficulty to find physical <br />
interpretation, tedious approaches for obtaining the FEM matrix equations, and challenge to <br />
prove that the proposed shortcut method is consistent with the proposed fundamental<br />
variational equation.<br />
<br />
'''Difficulty in Treating Non-self-adjoint fields'''<br />
<br />
Before 1980, most papers about variational formulation assume that the problem as an operator <br />
equation together with boundary conditions is self-adjoint. The inner product of a field with an <br />
operator operated on another field with associated boundary conditions is the same if we switch <br />
positions of the field and the operator. This reciprocity does not hold for a non-self-adjoint <br />
problem. For an example of the non-self-adjoint problem, consider the situation with <br />
anisotropic materials whose characteristics are described by non-symmetric and/or non�Hermitian matrices. <br />
<br />
The FEM@NTU team in 1980 first proposed a general variational formulation with an adjoint <br />
problem to handle a non-self-adjoint problem. The solution of the adjoint problem is related <br />
to problems with the material characteristics being the transpose or Hermitian of those of the <br />
original problem. Although the adjoint field is introduced, we still need to solve only the field <br />
distribution of the original problem with the FEM. The 1980 paper also provided physical <br />
interpretation through a concept of generalized reaction. However, it did not reveal how to <br />
extend the formulation for general exterior problems.<br />
<br />
'''Unsystematic derivation of variational formulation'''<br />
<br />
For mechanics, a variational equation is often obtained from the least action principle. For <br />
electromagnetics, the application of the FEM for exterior field problems is scarce before 1984.<br />
The most related papers are: Silvester and Hsieh (1971) [1], McDonald and Wexler (1972) [2], <br />
the Unimoment method (Mei, 1974) [3], and Morishita and Kumagai (1977) [4]. The variational <br />
equations in these works are derived case by case after setting up systems of partial differential <br />
equations from the Maxwell equation, except for Morishita and Kumagai in 1977, in which the <br />
formulation started from the least action principle generalized for electromagnetic fields. <br />
However, their approach is inconvenient and indirect for use since the formulation involves <br />
vector and scalar potentials.<br />
The FEM@NTU team first proposed in 1980 (primarily for interior problems and simple one�dimensional problems) [5] and 1984 (with extension to general exterior problems) [6] that the <br />
FEM equations for any linear Electromagnetic field problems can be deduced from setting the <br />
Fundamental Variational Principle (FVP) to be stationary, equivalent to the Maxwell equations<br />
along with the associated boundary conditions. Variational equations can be deduced simply <br />
by applying problem-dependent constraints to reduce the FVP. <br />
<br />
'''Difficulty in Dealing with Exterior Fields'''<br />
<br />
Silvester and Hsieh [1] applied Green's theorem to obtain a variational equation by treating the <br />
outer region as a single exterior element. However, they dealt with only 2D Laplace equations, <br />
i.e., static fields only. McDonald and Wexler [2] treated an Integral equation as a constraint to <br />
replace the exterior element. Their paper also shows that they can handle only 2-D Poisson <br />
equations, again, static fields only. Mei [3] proposed the unimoment method. He imposed an <br />
artificial boundary and expressed the exterior and interior fields as sums of eigenmodes and <br />
pseudo modes, respectively. A pseudo mode for the internal problem was obtained by the FEM <br />
with enforcing boundary conditions on the artificial boundary like an exterior eigenmode. The coefficients of both series were then acquired by matching the continuity conditions on the <br />
artificial boundary. The exterior field was not included in the variational equations directly.<br />
<br />
The FEM@NTU team expressed the exterior field in the following ways: a sum of eigenmodes <br />
(including scattering wave modes [6] and propagation modes in general waveguide [7]) or an <br />
integral over the artificial interior-exterior boundary [8]. Such expressions are then included<br />
in the functional with careful treatment for keeping their stationarity. In addition, the <br />
FEM@NTU team also proposed an attractive approach for dielectric waveguide problems. For <br />
such problems, 2-D transverse trial fields extending to infinity in the stationary functional are <br />
transformed into the inside of a closed region in the complex plane by a conformal mapping<br />
[9]. The exterior fields are thus taken into considerations automatically.<br />
<br />
'''Difficulty to Find Physical interpretation'''<br />
<br />
Many early publications about variational formulation describe their results with mathematic <br />
manipulation only. The variational principles derived by the FEM@NTU team in 1980 [5] and <br />
1984 [6] were with a physical interpretation of general reaction. Note also the stationarity of <br />
the FVP is equivalent to the Maxwell equations along with the boundary conditions, just like <br />
that the principle of virtual work is equivalent to Newton's laws in statics and dynamics. Also,<br />
in the 1984 paper [6], the FVP can be reduced to a form as oscillatory power if the problem is <br />
self-adjoint, which is similar to the least action principle for mechanics.<br />
<br />
'''Tedious Approaches for Obtaining the FEM matrix equations'''<br />
<br />
The process of obtaining a FEM matrix equation from the FVP by applying problem-related <br />
constraints and the Ritz procedure are pretty tedious, though systematic. The FEM@NTU <br />
team's 1985 paper introduced the Variational Reaction Theory (VRT) [10] to derive the required <br />
matrix equation and found it a generalization of the conventional Galerkin's method. <br />
<br />
'''Difficulty in Proving the Shortcut Being Consistent with the Fundamental Variational <br />
Equation'''<br />
<br />
The stationarity of the FVP proposed in 1984 [6] is equivalent to the Maxwell equations and <br />
should hold for all linear electromagnetic field problems. The VRT [10] is more efficient in <br />
deriving the required FEM matrix equations. However, its consistency with the variational <br />
equation of FVP was not clear. In other words, why does the generalized Galerkin's method <br />
work? Why does the way to deal with the exterior field in the generalized Galerkin's method <br />
lead to the correct solution? Such essential theoretical questions were answered in a FEM@NTU <br />
paper in 1988, in which the team proposed the concept of the Partial Variational Principle (PVP) <br />
[11]. By PVP, the variation on a functional of trial field f and its adjoint f<sup>a</sup>, like the partial <br />
differentiation, equals the sum of two functionals (PVPs), where one is obtained by taking partial <br />
variation with respect to f while the other is taken with respect to f<sup>a</sup>. If only field f is to be solved, <br />
the functional by taking partial variation to f can be ignored. The resultant partial variational <br />
principle is just the same as the starting equation of VRT. The consistency of VRT and the <br />
variational equation on the FVP is thus proved.<br />
|a5=Features of this series of work are given below:<br />
#First variational formulation equivalent to the Maxwell equations and associated boundary conditions. Also proposed are their physical interpretations.<br />
#A systematic approach to derive the FEM matrix equations.3. First inclusion of exterior field in the variational equation, which leads to the now popular hybrid finite element method.<br />
#First shortcut to derive the FEM matrix equations directly, which is equivalent to a generalized Galerkin's method and widely used in academic and commercial software development circles.<br />
#A conformal mapping technique for dielectric waveguide problems to transform the two-dimensional transverse field into the inside of a closed region. Solving the fields in this closed region by the FEM handles the exterior fields automatically.<br />
<br />
'''Later development'''<br />
<br />
Since the FEM@NTU team published their 1985 papers, the generalized Galerkin's method <br />
becomes very popular in solving the scattering of objects in free space and waveguide <br />
structures. The primarily related papers are those introducing the transfinite element method <br />
(Lee and Cendes, 1987, 1987 [12], [13]; Cendes and Lee, 1988 [14]; Lee, Sun, and Cendes, 1991<br />
[15]), and those emphasizing hybrid finite element methods for the scattering of objects in free <br />
space (Jin and Liepa, 1988 [16]; Jin and Liepa, 1988 [17]). The transfinite element method was <br />
then applied for developing the commercial software HFSS for dealing with RF, microwave, and <br />
millimeter-wave circuits. The hybrid finite element method has also been proved efficient and <br />
effective in solving realistic scattering problems (for example, Jin and Volakis, 1991 [18] and <br />
Shen et al., 1998 [19]). However, the impact of the generalized Galerkin's method is not limited <br />
by its applications to solving electromagnetic wave problems with the finite element methods. <br />
Professor Jin-Fa Lee at the Ohio State University also recognized the strong correlation of the <br />
generalized Galerkin's method with the reciprocity theorem in electromagnetic fields and the <br />
popular Bi-CG methods for solving complex symmetric but non-Hermitian matrices equations.<br />
<br />
'''The FEM@NTU team'''<br />
<br />
The FEM@NTU leader, Professor Chen, is the first faculty in Taiwan who published papers in <br />
IEEE journals (as early as 1970 [20]). He and his students published their first FEM paper on <br />
applying the FEM to a one-dimensional problem with inhomogeneous dielectric in free space <br />
in 1979 [21], [22] and a rectangular waveguide in 1981 [23]. Later the FEM@NTU team began <br />
to focus on finding a general variational equation for electromagnetic field problems. They <br />
published papers on the fundamental variational principles (FVP) in 1980 [5] and 1984 [6], <br />
respectively. A shortcut, the VRT, for deriving FEM matrix equations from the FVP was then <br />
proposed in their 1985 paper [10]. Finally, in 1988, the FEM@NTU team proposed the partial <br />
variational principle [11] and proved that the VRT is consistent with the variational equation on <br />
the FVP.<br />
<br />
Not restricted to pure and abstract mathematic formulation, based on the FVP, VRT, and PVP, <br />
Professor Chen and his students published various applications. The applications include: the <br />
scattering of the perfect electric conductor (PEC) cylinder with inhomogeneous dielectric <br />
coating [6], general scattering from anisotropic inhomogeneous slabs [24], [25] and cylinders<br />
[26], scattering from a magnetostatic slab in parallel-plate waveguide [7], general analysis of <br />
dielectric waveguides [8], [10], birefringence analysis of anisotropic optical fibers [27], and <br />
analysis of discontinuities in a dielectric waveguide [11] and planar dielectric waveguides [28], <br />
and planar dielectric antennas [29], For weakly guiding dielectric waveguides [9], microstrip lines<br />
[30], [31], and coplanar waveguides [32], [33], the FEM@NTU team conceived a delicate idea, <br />
the Variational Conformal Mapping technique [9], to transform the problem onto a complex <br />
plane, and wherein solve a scalar field.<br />
<br />
'''Further information'''<br />
<br />
Jin-Fa Lee is the major developer of the booming commercial software HFSS. He took <br />
Professor Chen's course on mathematical physics, which introduced variational formulation <br />
coupled with the FEM in 1981 when he was an undergraduate student in the National Taiwan <br />
University's electric engineering department. Afterward, he pursued his Ph.D. studies at<br />
Carnegie Mellon University under the supervision of Professor Zoltan J. Cendes, father of HFSS <br />
and the founder of Ansoft Corp. Note Ansoft Corp. was later acquired by Ansys Corp.<br />
|submitted=No<br />
}}</div>Administrator1http://ieeemilestones.ethw.org/index.php?title=Milestone-Proposal:Theoretical_Foundation_of_Finite-Element-Method_for_Electromagnetics&diff=11150Milestone-Proposal:Theoretical Foundation of Finite-Element-Method for Electromagnetics2021-06-14T14:27:53Z<p>Administrator1: Created page with "{{Proposal |litigation=No |more than 25 years=Yes |within fields of interest=Yes |benefit to humanity=Yes |regional importance=Yes |ou is paying=Yes |ou is arranging dedicatio..."</p>
<hr />
<div>{{Proposal<br />
|litigation=No<br />
|more than 25 years=Yes<br />
|within fields of interest=Yes<br />
|benefit to humanity=Yes<br />
|regional importance=Yes<br />
|ou is paying=Yes<br />
|ou is arranging dedication=Yes<br />
|section is taking responsibility for plaque=Yes<br />
|a11=Yes<br />
|a3=1979 -1991<br />
|a1=Theoretical Foundation of Finite-Element-Method for Electromagnetics<br />
|plaque citation=From 1979 to 1991, an electromagnetic-wave research group in the department of electrical <br />
engineering, National Taiwan University, laid the theoretical foundation for the Finite Element <br />
Method for general linear Electromagnetic field problems. They also found a straightforward<br />
derivation as a generalized Galerkin's method. It has been widely applied in academic <br />
researches and commercial software development, like the early versions of HFSS.<br />
<br />
1979 至 1991 期間，台大電機系的電波研究團隊建構了應用於一般線性電磁學問題的有限元素<br />
法理論基礎。他們也發現有限元素法的矩陣方程式，可以由推廣的 Galerkin 方法直接完成。這種<br />
推廣的 Galerkin 方法很快就應用到許多學術研究以及廣為應用的商業模擬軟體開發，如 HFSS。<br />
|a2b=IEEE Taipei Section<br />
|IEEE units paying={{IEEE Organizational Unit Paying<br />
|Unit=IEEE Taipei Section<br />
|Senior officer name=Kea-Tiong Tang, Chairman<br />
}}<br />
|IEEE units arranging={{IEEE Organizational Unit Arranging<br />
|Unit=IEEE Taipei Section<br />
|Senior officer name=Kea-Tiong Tang, Chairman<br />
}}<br />
|IEEE sections monitoring={{IEEE Section Monitoring<br />
|Section=IEEE Taipei Section<br />
|Section chair name=Kea-Tiong Tang, Chairman<br />
}}<br />
|Milestone proposers={{Milestone proposer<br />
|Proposer name=Shyh-Kang Jeng, Ruey-Beei Wu, and Jin-Fa Lee<br />
|Proposer email=skjeng@ntu.edu.tw, rbwu@ntu.edu.tw, and jin.fa.lee.1863@gmail.com<br />
}}<br />
|a2a=Department of Electrical Engineering, National Taiwan University, 1, Sec. 4, Roosevelt Rd., Taipei, Taiwan 10617. GPS coordinates: x 25.01953, y 121.54410<br />
|a7=The intended site is inside the main department building, which started its construction when Professor Chun Hsiung Chen, the team leader for the proposed milestone, served as the department head from 1982 to 1985. In this building, Professor Chen and his students in the team taught and developed further applications of the milestone. However, the major works of the proposed milestone were conducted earlier in the now civil engineering building, about 600 meters away. This building now accommodates more than 2500 students, including 800 undergraduates, 1200 master, and 500 Ph.D. students, reside to study various areas in electrical engineering. It is the "powerhouse" in Taiwan to promote the innovation, education, and promotion of electrical engineering for humanity.<br />
|a8=The original buildings where the development took place now serve a different goal, are no longer publicly accessible, and will probably be demolished within a few years.<br />
|mounting details=The intended location is near the entrance of the auditorium in the building, where the seminars, conferences, and invited lectures are frequently held. A picture giving an overview of the entrance of the auditorium is shown below. The IEEE can consult the department of Electrical Engineering about the exact place and mounting within the building<br />
|a9=The building is opened on weekdays. The site is protected/secured by a management team and security cameras.<br />
|a10=Chairman Chung-Chih Wu, Department of Electrical Engineering, National Taiwan University<br />
|a4=The Finite-Element Method (FEM) has been popular in modeling linear electromagnetic fields, <br />
from radiation, scattering, waveguide, to high-frequency circuits. To get a matrix equation for <br />
FEM, we have to derive a variational equation first. The applications of finite element methods <br />
for static fields were understood, and the variational nature of the formulation was well <br />
documented. However, for electromagnetic wave radiations and scattering problems, the <br />
underlying physics is non-Hermitian, and the corresponding variational principle was lacking in <br />
the 1980s. <br />
<br />
Consequently, the work's significance is: proposing a systematic method for derivation of <br />
variational equations, including exterior fields in the variational equations, and discovering a <br />
shortcut for deriving the FEM matrix equations directly. The inclusion of exterior field results in <br />
the popularity of the hybrid element method, and the shortcut method was a generalized <br />
Galerkin's method. Such a shortcut and the hybrid finite element method have been widely <br />
used for academic research and successful commercial software development, like the early <br />
versions of HFSS software (High-Frequency Structure Simulation).<br />
|a6=The major obstacles needed to be overcome by the FEM team led by Professor Chun Hsiung <br />
Chen (FEM@NTU) are: difficulty in treating non-self-adjoint fields, unsystematic methods for <br />
the variational formulation, difficulty in dealing with exterior fields, difficulty to find physical <br />
interpretation, tedious approaches for obtaining the FEM matrix equations, and challenge to <br />
prove that the proposed shortcut method is consistent with the proposed fundamental<br />
variational equation.<br />
<br />
'''Difficulty in Treating Non-self-adjoint fields'''<br />
<br />
Before 1980, most papers about variational formulation assume that the problem as an operator <br />
equation together with boundary conditions is self-adjoint. The inner product of a field with an <br />
operator operated on another field with associated boundary conditions is the same if we switch <br />
positions of the field and the operator. This reciprocity does not hold for a non-self-adjoint <br />
problem. For an example of the non-self-adjoint problem, consider the situation with <br />
anisotropic materials whose characteristics are described by non-symmetric and/or non�Hermitian matrices. <br />
<br />
The FEM@NTU team in 1980 first proposed a general variational formulation with an adjoint <br />
problem to handle a non-self-adjoint problem. The solution of the adjoint problem is related <br />
to problems with the material characteristics being the transpose or Hermitian of those of the <br />
original problem. Although the adjoint field is introduced, we still need to solve only the field <br />
distribution of the original problem with the FEM. The 1980 paper also provided physical <br />
interpretation through a concept of generalized reaction. However, it did not reveal how to <br />
extend the formulation for general exterior problems.<br />
<br />
'''Unsystematic derivation of variational formulation'''<br />
<br />
For mechanics, a variational equation is often obtained from the least action principle. For <br />
electromagnetics, the application of the FEM for exterior field problems is scarce before 1984.<br />
The most related papers are: Silvester and Hsieh (1971) [1], McDonald and Wexler (1972) [2], <br />
the Unimoment method (Mei, 1974) [3], and Morishita and Kumagai (1977) [4]. The variational <br />
equations in these works are derived case by case after setting up systems of partial differential <br />
equations from the Maxwell equation, except for Morishita and Kumagai in 1977, in which the <br />
formulation started from the least action principle generalized for electromagnetic fields. <br />
However, their approach is inconvenient and indirect for use since the formulation involves <br />
vector and scalar potentials.<br />
The FEM@NTU team first proposed in 1980 (primarily for interior problems and simple one�dimensional problems) [5] and 1984 (with extension to general exterior problems) [6] that the <br />
FEM equations for any linear Electromagnetic field problems can be deduced from setting the <br />
Fundamental Variational Principle (FVP) to be stationary, equivalent to the Maxwell equations<br />
along with the associated boundary conditions. Variational equations can be deduced simply <br />
by applying problem-dependent constraints to reduce the FVP. <br />
<br />
'''Difficulty in Dealing with Exterior Fields'''<br />
<br />
Silvester and Hsieh [1] applied Green's theorem to obtain a variational equation by treating the <br />
outer region as a single exterior element. However, they dealt with only 2D Laplace equations, <br />
i.e., static fields only. McDonald and Wexler [2] treated an Integral equation as a constraint to <br />
replace the exterior element. Their paper also shows that they can handle only 2-D Poisson <br />
equations, again, static fields only. Mei [3] proposed the unimoment method. He imposed an <br />
artificial boundary and expressed the exterior and interior fields as sums of eigenmodes and <br />
pseudo modes, respectively. A pseudo mode for the internal problem was obtained by the FEM <br />
with enforcing boundary conditions on the artificial boundary like an exterior eigenmode. The coefficients of both series were then acquired by matching the continuity conditions on the <br />
artificial boundary. The exterior field was not included in the variational equations directly.<br />
<br />
The FEM@NTU team expressed the exterior field in the following ways: a sum of eigenmodes <br />
(including scattering wave modes [6] and propagation modes in general waveguide [7]) or an <br />
integral over the artificial interior-exterior boundary [8]. Such expressions are then included<br />
in the functional with careful treatment for keeping their stationarity. In addition, the <br />
FEM@NTU team also proposed an attractive approach for dielectric waveguide problems. For <br />
such problems, 2-D transverse trial fields extending to infinity in the stationary functional are <br />
transformed into the inside of a closed region in the complex plane by a conformal mapping<br />
[9]. The exterior fields are thus taken into considerations automatically.<br />
<br />
'''Difficulty to Find Physical interpretation'''<br />
<br />
Many early publications about variational formulation describe their results with mathematic <br />
manipulation only. The variational principles derived by the FEM@NTU team in 1980 [5] and <br />
1984 [6] were with a physical interpretation of general reaction. Note also the stationarity of <br />
the FVP is equivalent to the Maxwell equations along with the boundary conditions, just like <br />
that the principle of virtual work is equivalent to Newton's laws in statics and dynamics. Also,<br />
in the 1984 paper [6], the FVP can be reduced to a form as oscillatory power if the problem is <br />
self-adjoint, which is similar to the least action principle for mechanics.<br />
<br />
'''Tedious Approaches for Obtaining the FEM matrix equations'''<br />
<br />
The process of obtaining a FEM matrix equation from the FVP by applying problem-related <br />
constraints and the Ritz procedure are pretty tedious, though systematic. The FEM@NTU <br />
team's 1985 paper introduced the Variational Reaction Theory (VRT) [10] to derive the required <br />
matrix equation and found it a generalization of the conventional Galerkin's method. <br />
<br />
'''Difficulty in Proving the Shortcut Being Consistent with the Fundamental Variational <br />
Equation'''<br />
<br />
The stationarity of the FVP proposed in 1984 [6] is equivalent to the Maxwell equations and <br />
should hold for all linear electromagnetic field problems. The VRT [10] is more efficient in <br />
deriving the required FEM matrix equations. However, its consistency with the variational <br />
equation of FVP was not clear. In other words, why does the generalized Galerkin's method <br />
work? Why does the way to deal with the exterior field in the generalized Galerkin's method <br />
lead to the correct solution? Such essential theoretical questions were answered in a FEM@NTU <br />
paper in 1988, in which the team proposed the concept of the Partial Variational Principle (PVP) <br />
[11]. By PVP, the variation on a functional of trial field f and its adjoint f<sup>a</sup>, like the partial <br />
differentiation, equals the sum of two functionals (PVPs), where one is obtained by taking partial <br />
variation with respect to f while the other is taken with respect to f<sup>a</sup>. If only field f is to be solved, <br />
the functional by taking partial variation to f can be ignored. The resultant partial variational <br />
principle is just the same as the starting equation of VRT. The consistency of VRT and the <br />
variational equation on the FVP is thus proved.<br />
|submitted=No<br />
}}</div>Administrator1http://ieeemilestones.ethw.org/index.php?title=New_Accounts_Temporarily_Disabled&diff=11137New Accounts Temporarily Disabled2021-06-09T13:30:56Z<p>Administrator1: </p>
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<div>Account creation is temporary disabled on the Milestones wiki. <br />
<br />
If you do not have an account and would like to submit a Milestone Proposal, '''please email n.w.brewer@ieee.org''' with a Milestone proposal form, either fully or partially completed.<br />
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If you do not have an account and would like to comment on an existing Milestone Proposal, '''please email n.w.brewer@ieee.org''' with your comments.</div>Administrator1http://ieeemilestones.ethw.org/index.php?title=New_Accounts_Temporarily_Disabled&diff=11136New Accounts Temporarily Disabled2021-06-09T12:42:59Z<p>Administrator1: Administrator1 moved page Accounts Temporarily Disabled to New Accounts Temporarily Disabled without leaving a redirect</p>
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<div>Account creation is temporary disabled on the Milestones wiki. If you do not have an account and would like to submit a Milestone Proposal, please email n.w.brewer@ieee.org with a Milestone proposal form, either fully or partially completed.</div>Administrator1http://ieeemilestones.ethw.org/index.php?title=New_Accounts_Temporarily_Disabled&diff=11135New Accounts Temporarily Disabled2021-06-09T12:42:48Z<p>Administrator1: Created page with "Account creation is temporary disabled on the Milestones wiki. If you do not have an account and would like to submit a Milestone Proposal, please email n.w.brewer@ieee.org wi..."</p>
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<div>Account creation is temporary disabled on the Milestones wiki. If you do not have an account and would like to submit a Milestone Proposal, please email n.w.brewer@ieee.org with a Milestone proposal form, either fully or partially completed.</div>Administrator1http://ieeemilestones.ethw.org/index.php?title=Milestone-Proposal:MPEG_integrated_circuits&diff=11111Milestone-Proposal:MPEG integrated circuits2021-06-03T18:43:08Z<p>Administrator1: Administrator1 moved page Milestone-Proposal:SGS-THOMSON MPEG integrated circuits to Milestone-Proposal:MPEG integrated circuits</p>
<hr />
<div>{{Proposal<br />
|docketid=2021-10<br />
|litigation=No<br />
|more than 25 years=Yes<br />
|within fields of interest=Yes<br />
|benefit to humanity=Yes<br />
|regional importance=Yes<br />
|ou is paying=Yes<br />
|ou is arranging dedication=Yes<br />
|section is taking responsibility for plaque=Yes<br />
|a11=Yes<br />
|a3=1986<br />
|a1=Multimedia Integrated Circuits for MPEG, 1986<br />
|plaque citation=THOMSON (now STMicroelectronics) pioneered the family of multimedia integrated circuits, accelerating Moving Picture Experts Group (MPEG) standards. Discrete Cosine Transform designed with ENST (now Telecom ParisTech) was the first. Innovative memory reduction techniques, highly optimized dedicated hardware accelerators, super-integration of heterogeneous processor units achieved significant performances and cost reduction with minimized energy consumption. These integrated circuits were the key enablers of digital multimedia services to entertain end-users in everyday life.<br />
|a2b=France Section<br />
|IEEE units paying={{IEEE Organizational Unit Paying<br />
|Unit=France<br />
|Senior officer name=Claire LAJOIE-MAZENC<br />
|Senior officer email=claire.lajoie-mazenc@rte-france.com<br />
}}<br />
|IEEE units arranging={{IEEE Organizational Unit Arranging<br />
|Unit=France with STMicroelectronics<br />
|Senior officer name=Claire LAJOIE-MAZENC<br />
|Senior officer email=claire.lajoie-mazenc@rte-france.com<br />
}}<br />
|IEEE sections monitoring={{IEEE Section Monitoring<br />
|Section=France<br />
|Section chair name=Claire LAJOIE-MAZENC<br />
|Section chair email=claire.lajoie-mazenc@rte-france.com<br />
}}<br />
|Milestone proposers={{Milestone proposer<br />
|Proposer name=Danilo Pau<br />
|Proposer email=danilo.pau@st.com<br />
}}{{Milestone proposer<br />
|Proposer name=Jean-Michel Moutin<br />
|Proposer email=jean-michel.moutin@st.com<br />
}}<br />
|a2a=(45.203333, 5.695833)<br />
|a7=The Grenoble site is of premier importance for STMicroelectronics. It was owned by THOMSON SEMICONDUCTEURS, then merged with SGS in 1987 to form SGS-Thomson (now STMicroelectronics). Nowadays is the biggest R&D site of the company, hosting many product divisions from the three Product Groups of the company, including silicon and software design, test, and advanced packaging developments. In this site MPEG chips were conceived and designed<br />
|a8=Yes, even if part of them were restructured they still exists @ STMicroelectronics, 12, rue Jules Horowitz F-38000 Grenoble, France<br />
|mounting details=Plaques will be installed in a public place at the main entrance as shown in figure 1. It will be in front of company security personnel who are monitoring entrance 24 hours in a day, every day in a year. Very close as indicated there is the public road. Plaque will be placed at 12, rue Jules Horowitz F-38000 Grenoble, France. GPS coordinates are: 45°12’12” N ; 05°41’45” E (45.203333, 5.695833). Therefore, interested visitors will not need to be escorted by the company security personnel to watch the plaque or to take a photo with it. The milestone plaque will be installed right in front of the main entrance access. It is where employees, visitors and customers must pass through to get into the Grenoble offices on daily basis. It is monitored continuously 24h/7d by security human resources and surveillance camera. It is a public place, right outside the site restricted perimeter.<br />
|a9=It is protected by company security human resources and with surveillance camera, 24h/7d. It is publicly and easily accessible from 12, rue Jules Horowitz F-38000 Grenoble, France. The site can be reached also from Lion Airport, close to Grenoble as shown in figure 2.<br />
|a10=STMicroelectronics (Grenoble 2) SAS<br />
|a4=[[image:Figure1 Placque installation.jpg|thumb|Figure 1 Candidate place for plaque installation]]<br />
<br />
[[image:Figure2b.jpg|thumb|Figure 2 How to get the plaque from Lyon airport]]<br />
<br />
Since mid 80s the technology objective of STMicroelectronics was to conceive, ahead of MPEG standards, and introduce innovative hardware solutions to be produced in high volumes, able to achieve several order of magnitude speed acceleration, compared to unfeasible, hypothetical, very costly full software implementation of MPEG decoding and encoding functionalities, by introducing for the first time very advanced techniques such as RAM memory compression, reductions and associated embedding on chip, dedicated and customized hardware implementations in order to save precious silicon area per technology node being used (starting from 2um and the next ones), super integrate new functionalities, as the needs evolved in the next 30 years, in a less than a watt power envelope. <br />
The DCT (discrete cosine transform forward and backward) integrated circuit, the first in the family, was designed to be very reliably and produced in mass volumes such that was subsequently used in the Cassini-Huygens probe for transmitting compressed images of Saturn for 20 years. This is the most important proof that the integrated circuits was very resilient to cosmic rays and therefore also for on earth multimedia entertainment applications.<br />
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Specific objectives, that motivated STMicroelectronics (short name ST) to pioneer Mpeg family of System on a Chips and pursue associated CMOS silicon technology developments to implement it and starting since 1986 and onward, were:<br />
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1) To create reliable and low complex digital CMOS building (integrated circuits) blocks at mass production maturity to dramatically accelerate real time MPEG video decoding and encoding functionalities at increasing image resolutions and frame rates.<br />
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2) To super-integrate such building blocks in more complex integrated circuits and SoCs to accelerate MPEG 1, 2, 4, H264, HEVC and subsequent standardized MPEG specifications, at the same time they were under development by ISO/IEC SC29 WG11 (known as MPEG committee). In other words before the standards were officially frozen and be formally published.<br />
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3) To achieve lowest on chip memory footprint and bit-depth of computing data paths to dramatically save silicon area given the existing (from 2µm bulk to 25nm FDSOI) ST CMOS technology constraints for mass production and reliable manufacturability with marginal chip defectivity.<br />
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4) To achieve minimal power consumption, to and below 1W across different silicon technologies generations and starting from 2um silicon gate manufacturing processes. Successive lower dimension lithography, were needed considering an increasing need to super integrate functionalities, heterogeneous hardware accelerators, microprocessors, graphic engines, crypto engines, a rich set of peripherals and interfaces etc. ST developed in house all subsequent CMOS technologies such as 0.5um, 0.35um up to the most sophisticated 25nm FDSOI, fully depleted silicon on insulator) needed to sustain the pace of super integrating the functionalities. <br />
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5) To remove any need of costly and bulky heat-sinks as well as complex and motorized cooling mechanisms to offer an easier viable integration into thinner and very cheap video equipment manufactured systems with very affordable costs.<br />
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6) To dramatically reduce as low as possible video communication bandwidth between the chip and the external DRAM memories to minimize memory requirements of those chips and associated costly power consumption.<br />
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7) To control those chips with very simple and low computing power 8bits micro controllers and incrementally (as requirements has grown) with more sophisticated 32 bits: this to support flexibility and complex operating systems that required further software computing needs to offer un precedented user experience, multitasking and programmability. Including the use of advanced graphics to ease content accessibility and fruition.<br />
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8) To enable viable, widely adopted, broad range of diversified digital multimedia applications and services, implying affordable software developments and deployments to a huge range of end users at worldwide level with different regional languages, habits and needs.<br />
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In the following, there is the summary of achievements by STi (no named by ST) family of integrated circuits subject of the present milestone proposal. To meet the above-mentioned challenging objectives and long-term technology vision, ST, since 1986, has developed following key innovative technologies and chips. A few but very relevant set of them will be described, because the family is too huge to report completely in this document because was spanning in 30 years of intense and diversified developments.<br />
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1) Seminal work on ST CMOS technologies, started at ENST [1.24] [1.25] [7.0] with Thomson Semiconductors (now STMicroelectronics), to produce the architecture of an economically viable chip implementing various DCY block sizes 16x16, 16x8, 8x8, 8x4, 4x4 very ahead of the requirements MPEG will specify in the subsequent years . The main features of the chip under development with THOMSON SEMICONDUCTEURS was using 2 µm CMOS lithography first and next 1.25 µm CMOS technology . Design was embodying 70,400 Transistors, in 25 mm2, with Internal clock 13.5 MHz, forward and backward DCT, 8 bits pixels, 16 bits internal accuracy. The chip was sampled by THOMSON SEMICONDUCTEUR in October 1987.<br />
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2) Then STV3200 [1.1] [1.2] was a dedicated integrated circuit to accelerate the discrete cosine transform (DCT). The two-dimensional forward DCT (FDCT) and inverse DCT (IDCT) was implemented for various image block sizes and the pixel rate was up to 15.0 MHz The circuit architecture was fully bidirectional with a 9-bit magnitude pixel data bus and a 12-bit magnitude coefficient data bus programmed as input or output depending on the selection of Forward DCT or Inverse DCT function. DCT was so complex that to be implemented on a CPU required about 1 billion additions per second (1 giga Hertz operations per second) to process moving pictures in real time. CPUs and CMOS silicon process were unable to achieve such a very high frequency, equivalently implying the computing power of fifty Motorola 68020 [2.1], one of the faster micro-processors in the 1980s. The integrated circuit went officially in production at the end of 1987 and was a world premiere product. Since 1988, this component was successfully sold by SGS-Thomson. It implemented key patents [4.1][4.2] for rearranging, permuting or selecting data according to predetermined rules, for changing the order of data flow, e.g. matrix transposition, LIFO (last in first out) buffers; internally compensating and handling overflow or underflow that was key for DCT and IDCT accurate and reliable implementations.<br />
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Innovative memory footprint reduction and distribution techniques were used since the hardware design did not use the traditional architecture (such as a unique multiplier that would read/write in a large memory), but a bit-serial pipelined architecture, where dynamic memory was distributed across the chip, to feed the 16 bit/serial dedicated multipliers that the chip had.<br />
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The STV3200 chip was considered so reliable the was used in the DISR (descent imager) [1.26] [2.9] [7.0] of Cassini-Huygens probe, therefore subject of cosmic rays interactions, that was launched in 1997 and has transmitted wonderful images of Saturn planet until 2017. All those historic images that are available in this website [2.10] have been processed through the STV3200 for 10 years through the solar system!<br />
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Design of the STV3200 happened during the December 1986 to August 1987 period (product sampling around October 1987) as mentioned at the end of [1.25]. As said commercialization of the STV3200 started in 1988. It must be noted that on November 1988 there was the publication of the H261 standard (1st standard using DCT for real time video coding) while on May 1988 there was the 1st meeting of the MPEG standard (that was published in 1993) using block based DCT. This chip was considered as proof of implementation by MPEG ad-hoc group<br />
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[[image:Figure3 dct chip.jpg|thumb|Figure 3a DCT chip package]]<br />
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[[image:Figure3b.png|thumb|Figure 3b DCT chip layout]]<br />
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3) STi3220 [1.3] [1.4] [1.5] was the second member of the family, a real time motion estimation integrated chip dedicated to motion estimation at video rates. The chip was optimized to compute the displacement vector of variable size 8x4n or 16x4n pixel blocks in a search window, and between temporally distant pictures, defined by a maximum horizontal and vertical displacement of +7/-8 pixels corresponding to 256 different vectors. The chip computed 256 distortions for each block search according to the MAE (mean absolute error) criteria. The motion estimation required about 4 billion of additions per second (4 giga Hertz operations per second). If it would be hypothetically implemented on micro processor it would require the equivalent computing power of several hundred of Motorola 68020. Therefore, it was unfeasible in software. Its development started in 1988, went in production and has been sold by SGS-Thomson since 1989. This component was another world premiere product in conjunction with STV3200. Furthermore, the Motion estimation processor was a key building block to accelerate more complex MPEG-2 Video Encoders [1.17]. Further innovative algorithms and hw design were conceived to remove any dependence from the block based search windows estimation, therefore reducing computational complexity as well as being able to accurately estimate real life motion [1.27] [1.28]. Cache based motion estimation was possible due to the recursive algorithms we invented and was designed to avoid block based data fetching with highly on chip data reusability therefore reducing memory bandwidth. [4.12] [4.13]<br />
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4) Super integration of those fundamental functions with others fundamental building blocks (e.g. scalar quantization and de-quantization, entropy coding and decoding as later needed by MPEG standard, motion compensation, unified dynamic memory management), was the next essential step required to manufacture reliable cheap system solutions for mass production and broad adoption while before they were consisting of few non integrated chips. In this respect [1.20] presents the deployment of STV3200 and STi3220 in a complete video codec hardware architecture for high pixel rates addressing standard (SD) and high definition (HD) picture formats.<br />
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5) STi3240 [1.18] was the 1st MPEG1/H261 chip with STV3208 (DCT processor) [1.19] supporting video decoding schemes up to 10 Mbit/s of the ISO/MPEG future (at that time under active definition) video standard and CCITT/H261 recommendation at video rate (352x288 pixels at 30fps). It required between 512 K Bytes up to 4Mbytes of external costly power hungry DRAM with a 8/16 bits microprocessor interface. External DRAM was a scarce and costly resource, dramatically impacting the overall power consumption by order of magnitude and bill of material. Therefore, the use of on the fly/real time memory reduction/compression techniques to support high chip calculations throughput and minimized data bandwidth between the chip and the memory were conceived and applied by ST for the first time and implemented. The fundamental idea behind the introduction of these techniques was to let MPEG compression noise to hide the one implied by the on the fly lossy compression generated by the memory reduction. countless tests at different bit rates (1.5, 4, 8, 16 mbit/s) confirmed the goodness of the idea as well as the deployment into multimedia systems sold for many years.<br />
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[[image:Figure4 decoder figure.png|thumb|Figure 4 decoder system, STV3208 was DCT co processor]]<br />
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6) Then the system on chip super integration era started with active developments. Earliest members of the STi digital multimedia chip family for mpeg moving picture processing were: STi3400, STi3500, STi3520A. Other early examples were STi7000, STi5000 (and the very many others that followed for 30 years of developments and market adoption). They were the first able to offer a dramatic reduction in silicon and package size, power consumption, memory usage with higher level of transistors integration, functionalities, and lowest cost of equipment’s. Such equipment’s were made previously by many discrete signal processors (DSP), making the system architecture very redundant, and which were placed into too many more boards. They were far from being viable from a mass manufacture point of view and cost affordable for MPEG-1 and MPEG-2 standards deployment at end user side. STi chips were very instrumental to accelerate the introduction to the end users of CD-ROM, DVDs, Set Top Box and digital TVs home systems that became ubiquitously adopted throughout the digital entertainment world and in everyone home (and mobile phones) across 3 decades all over the world.<br />
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7) Inside those chips’, innovative and advanced reduction techniques of external memory bandwidth were conceived and implemented first. They were key to lower power consumptions to and under 1W. In that respect several key methods are described in the following subsections:<br />
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a) block based pixel memory addressing and communication [4.3] allowed to minimize the cost of external memory page openings and closures, distributing the costly overhead per block size (composed by several pixels) instead of per single or per few pixels. In turn this allowed to avoid hardware pipeline stalls resulting to achieve very close to peak performances and resulting in a full motion interactive frame rates, clear picture decoding, free from block artefacts<br />
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b) compressed picture decoding on the fly [4.4] was a break-through technology to decompress the mpeg bitstream and motion compensate it at the same time while displaying MPEG B-pictures. This to avoid inefficient and further storage of them in the external frame buffer, thus resulting in a dramatic reduction of the external memory to only 16 Mbits for SD definition [1.20] within the memory bandwidth budget<br />
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c) frame buffer lossy compression [1.11] [4.5] was another key technology used to co-decompress on the fly I , P and B MPEG pictures by halving the associated external DRAM memory and the memory bandwidth without annoying picture artefacts. As before introduced, in STi solutions the memory reduction quantization noise was cleverly masked within the MPEG coding noise, resulting in not human perceivable and visible loss of quality. This allowed to reach 8 Mbits DRAM footprint in SD definition enabling super integration of 1 bit transistor per cell DRAM on the same chip, in a more competitive way than integrating 6 transistor per cell SRAM. therefore STi was the 1st to not require any additional external memory for the MPEG SD video decompression task. Moreover another kind of memory reduction was applied to HDTV decoders with even further benefits. [1.23] was novel method to reduce the external memory needed by STi MPEG-2 HDTV decoder architecture. The total amount of memory was reduced from 128 to 32 Mbits preserving very good picture quality. Furthermore, it required low hardware complexity increases of less than 5%, in 0.35 um ST silicon technology, the total decoder silicon area with respect to the standard decoder implementation.<br />
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8) The STi family implementation of the aforementioned ST comprehensive vision was very instrumental to create the digital Multimedia domain. That was made possible with those and many other chips we are not mentioning for space reason but that spanned across 30 years for ST engineering efforts. <br />
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It's important to underline that the pioneering development work began since 1986 [1.24] [1.26] among different and key French partners as proof of the passion, motivation, technical vision permeating the France R&D context:<br />
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1) Thomson Semiconductor (merged later into SGS-THOMSON, now STMicroelectronics) launched innovative circuit architecture studies for integrated for the Discrete Cosine Transform since 1986<br />
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2) ENST Paris (now Telecon ParisTech) was very active since 1986 in integrated circuit architectures for DCT [1.24] [1.25] single chip for video rates design.<br />
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3) Rennes Electronics Laboratory, expert in the field of image compression, built image transmission equipment between studios and digital recording.<br />
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Under the finance support of the DAII (that time French State Agency) these three laboratories collaborated to form a formidable team responsible for realizing the first DCT component (STV3200) and the Motion Estimation chip (STi3220). The DCT and Motion estimation chips existed thanks to the strong collaboration between SGS-Thomson and the public research lab of ENST.<br />
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Thus, on 1988, SGS-THOMSON finalized these seminal developments into production (with background developments since 1986 [1.24] [1.26] in Thomson Semiconductor) therefore creating the wave of key integrated circuits and SoC for MPEG deployment. By consequence it mastered at industrial level initially the 2 key components which made possible and economically viable the realization of more complex, reliable, ready for mass production, yet low cost and low power MPEG-1 and MPEG-2 encoders and decoder systems for the (mid 80s) for the not yet existing digital multimedia television markets. <br />
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9) Apple Computer was looking for a technology partner in the field of image compression. Since aware of above-mentioned developments, contacted SGS-THOMSON in 1988. The 68020 microprocessors was used from March 1987 to March 1992 and only used twice, once in the Macintosh II as a high-end processor, and then again with the Macintosh LC, as a low-end processor. However, it was too slow and inadequate to support real time video decoding functions as for MPEG decoding at interactive frames. By recognizing this key technical limit, the collaboration with SGS-Thomson was started, the first in its kind, to study and develop highly integrated set of components to provide video functions for Apple's microcomputers. That was a very advanced concept for that time. <br />
Therefore SGS-THOMSON entered into a partnership with Apple ATG (Avanced Technology Group) headed by Al Alcorn Apple Fellow. Thus, based on SGS-THOMSON understanding of 68020 limits and the contribution of innovative chip solutions from SGS-THOMSON background work, the first architecture of an integrated system for image compression was defined to support the MPEG1 standard: the STi3240 [1.18], STi3400 [1.6]. STi3400 was a real time video, super integrated with DCT, decompression integrated processor supporting MPEG-1 and H.261 standards. The digital output was for PAL 50Hz and NTSC 60 Hz interlaced displays.<br />
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10) Next leveraging its expertise, SGS-THOMSON started a background work with RCA, which ended in 1992 with the development of an MPEG2 video decoder, STi3500 [1.7] and subsequent STi3520 [1.8] enabling DirecTV broadcast. Those were other essential components at the heart of the revolutionary multimedia digital television services introduced firstly from the USA Digital Satellite DirectTV firm. SGS-THOMSON succeeded in delivering the first MPEG2 decoder in the world, much ahead of the Californian start-up C-CUBE. As such the STi3500 was the enabler of the first Digital TV broadcast ever, that was the key to the worldwide leadership of SGS-THOMSON in digital multimedia market. It must be noticed that C-Cube was funded on 1988 when SGS-THOMSON had already above-mentioned chips in production and when Thomson semiconductor started on 1986. <br />
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11) STi3500 was the real time video decompression integrated circuit supporting MPEG-1 and MPEG-2 standards at video rates up to 720x480x60Hz or 720x576x50Hz requiring minimal support from an external 8bit microcontroller (ST8) used only to initialize the chip, reducing the complexity of software and associated code footprint. It required only 1W of power consumption. The STi3500 was a success since achieved a turnover greater than $ 100M in less than 3 years as a sign of significant market adoption. In that chip STV3200 (which was super integrated) represented only 10% of the total silicon area. STi3520 on top of STi3500, used only 16Mbits memory and integrated audio decoder compliant with MPEG layers I and II supporting sampling rates of 32, 44.1 and 48 KHz. STI3520A [1.20] was a single chip for MPEG MP@ML video decoding in only 16 Mbit RAM integrated with STi4500 MPEG L1 and L2 Audio decoder and integrating on screen display generator. The chip was using 0.5µm CMOS SGS-THOMSON technology<br />
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12) STi7000 [1.12] [2.2] was an integrated system for High-Definition Television (HDTV), which combined an MPEG-2 decoder with a display and format converter onto one chip in 1998. As already introduced in point 5) the most advanced trick was the frame buffer memory reduction through tiny on chip on the fly compression engine based on scalar adaptive quantization allowing full HDTV pictures to be decoded and displayed with only 64 Mbits of external memory instead of 128 Mbits. Designed for use in HDTV and other digital TV receivers, set top boxes and PCs, the STi7000 was developed in collaboration with Thomson Multimedia, a strategic partner with whom SGS-THOMSON shared a joint design center in Grenoble, France. The chip incorporated all the 18 video formats defined by the ATSC (Advanced Television Systems Committee) and Grand Alliance specifications. STi7000 supported video rates of up to 1920 x 1088 x 30Hz interlaced or 1280 x 720 x 60Hz progressive. Built in 0.35-micron SGS-Thomson HCMOS6 silicon technology, the STi7000 also included interfaces for a host microcontroller, local SDRAM, standard or high-definition video output and D1 digitized video input. Next versions STi7100 [1.13] STi7200 [1.14] also integrated graphics engine and power powerful micro controllers. Next generation STi7108 had dual ST40-300 CPU host processors linked to a 256K L2 cache giving up to 2000 DMIPS performance and a total of 4000 DMIPS. A 3D graphics engine [1.15] enabled advanced Internet content and high-performance gaming. It was the first set-top box IC [1.16] in the market to combine 3D OpenGL-ES 2.0, OpenVG vector graphics, Ethernet, USB and e-SATA interfaces to connect Internet devices, DVR storage or external Flash or hard-disk (HDD) drives. <br />
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13) The STi5500 was the first member of back-end decoders for set-top boxes and DVD players. Compliant with MPEG-2 to decode its transport stream and convert it into sounds and images that sent to loudspeakers, monitors, TV screens and similar human interfaces. The STi5500 was the first integrated circuit in the world to incorporate not only all the circuitry required to handle all the back-end functions but also a 32-bit microprocessor. The built-in microprocessor had sufficient processing power to handle system-level functions as well as the managing the MPEG decoding function, so it eliminated the need for a separate system controller in most applications. Its super integration was the crucial factor and achieved immediate customers adoption. Since then, ST has developed even more powerful members including the STi5505, which is the first silicon chip in the world to integrate all the back-end functions of a DVD player. <br />
As demonstration of the innovation it brought in the field of digital multimedia entertainment , STi5500 won [5.1] from a field of nearly 300 nominations, the prestigious European IT PrizesPrize awarded by the European Commission in conjunction with Euro-CASE, the European Council of Applied Science and Engineering, for the development of products that are expected to play fundamental roles in helping European industry to increase its share of world markets.<br />
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Summarizing SGS-THOMSON STi gained its leadership position in the field of digital consumer multimedia decoder-type products for digital satellite TV and DVD players. Early members such as STV3200, STi3220, STi3240, STi3400, STi3500, STi3520A, STi7000, STi7100, STi7108, STi5500 SoC through the 80s, 90s and 2000 years continued for the development of digital multimedia applications at heart of the worldwide digital multimedia convergence of the TV services for everyday users, the world of telecommunications and the world of the PC. <br />
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Many other generations were manufactured across the years as shown in the next figure 5 even supporting complex operative systems such as Linux.<br />
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[[image:Figure5 chiproadmap.png|thumb|Figure 5]]<br />
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Interestingly it has to be noted that many decades later, the pioneering work that conducted to STV3200 represented less than 0.1% of the surface of the SoC (figure 6). <br />
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[[image:Figure6 chip integration.jpg|thumb|Figure 6 Super integration of DCT with other multimedia functions]]<br />
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STMicroelectronics has sold over 500,000,000 (cumulated) of those integrated systems worldwide. This figure undoubtedly demonstrates the pervasivity of STi family through the digital multimedia entertainment world. Figure 7 shows cumulative shipments of ST products per year basis to further support the statement.<br />
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[[image:Figure7 cumulative shipments.png|thumb|Figure 7]]<br />
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14) As proof of the high relevance of the proposed milestone a number of letter of supports were provided by key and well know experts in the field<br />
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a) A letter of endorsement [7.0] to ST milestone is provided by Nicolas Demassieux, today Senior Vice President of Research, Orange [2.3], and in 80s assistant professor at ENST (now Telecom ParisTech) working on very optimized VLSI implementations for signal processing, included the DCT processor.<br />
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b) A letter of endorsement [7.1] to ST milestone is provided by Leonardo Chiariglione [2.3], the undisputed father of MPEG ISO/IEC SC29 WG11 and the tireless driving force of MPEG standards for digitized video. Leonardo is unanimously considered at world wide level a genius since created a new way of enjoying music, with Leonardo Chiariglione’ s MP3 standard.<br />
As mentioned in the public article [6.1] with Leonardo Chiariglione, SGS-Thomson has been a big MPEG driver since it was the world's leading producer of MPEG-related ICs and supplied close to 70 percent of the world's MPEG-2 decoder chips. That was the result of the audiovisual vision that was shared by SGS-Thomson, Thomson Multimedia SA, Paris, and France's government. Also, Chiariglione noted, Thomson's U.S. subsidiary RCA was in the desperate need of MPEG chips for a huge order of 1st generation satellite TV decoders--a million set-top boxes for the Hughes-RCA DirecTV newborn system--and SGS-Thomson Microelectronics got the contract, as proof of its leading integrated circuits technology started since 1986.<br />
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c) A letter of endorsement [7.2] to ST milestone is provided by prof Fabio Rocca. Prof Fabio Rocca on 1969 was the pioneer on motion estimation and compensation technologies fundamental technologies being adopted by MPEG standards 20 years later.<br />
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d) A letter of endorsement [7.3] to ST milestone is provided by Hisafumi Yamada, past Sony USA TV CTO that prove the high innovation STi HDTV chips provided to ATV USA television.<br />
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e) A letter of endorsement [7.4] to ST milestone is provided by Sylvain Kritter, Product Director VIZYON with proven expertize on HW design.<br />
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f) A letter of endorsement [7.5] to ST milestone is provided by Professor Emeritus Virginio Cantoni, University of Pavia. Also Fellow of the IAPR since 1994 and Life Fellow of the IEEE (he was Fellow since 1997). In 2006 the President of the Italian Republic conferred to Professor Virginio Cantoni the title of ‘Commander of the Order of Merit of the Italian Republic’. Professor Virginio Cantoni is an exper of VLSI image processors exploiting reduced memory architectures<br />
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g) letter [7.6] of endorsement by Professor Emeritus Mariagiovanna Sami, Politecnico di Miano. Past Full Professor, Digital Systems. IEEE Life Member. Minerva prize for woman scientists, the Seymour Cray prize for contributions in the area of parallel processing, the Herbert A. Simon Gold Medal, assigned by the Society for Design and Process Science. Cavaliere della Repubblica Italiana (knight of the Italian republic). Member of the Italian National Science Academy (“Dei Quaranta”). Expert of high-performance, fault-tolerant array architectures for digital signal and image processing.<br />
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g) letter of endorsement by Professor Andrea Basso who has been active in ISO/IEC SC19 WG11 working group also known as MPEG for almost 25 years. Since 1990 while in EPFL in the group of Murat Kunt and then in AT&T Bell labs Holmdel NJ and AT&T Research Laboratories, Middletown, NJ, USA in the group of Barry Haskell, Professor Basso directly contributed the development of several MPEG standards starting from MPEG1 and MPEG2 till the most recent HEVC standard.<br />
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15) In the following years STi products on MPEG where the key enabling factor of a huge digital consumer ecosystem composed by many operators, equipment manufacturers, software developers and conditional access companies as shown in the next figure 6<br />
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[[image:Figure8 ecosystem.png|thumb|Figure 8 Worlds wide level ecosystem for digital multimedia services created thanks to STi family]]<br />
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16) As written in the EETimes article [2.4] “In the first shift or wave (referred to in the set-top box market) , which began about 1994, the boxes were simple channel-hopping devices for satellite and cable TV providers, Hatch explained. (ST's MPEG-2 video decoders were used then in the boxes manufactured by Thomson's RCA subsidiary.)” which clearly witness ST was ahead.<br />
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17) As written in the EDN article [2.5] on 1996 “Dataquest has confirmed SGS-THOMSON Microelectronics (Lincoln, MA) as the world's leading supplier of MPEG decoder ICs in 1995.” which witnessed ST leadership on MPEG decoders.<br />
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18) as written into a public article STMicroelectronics NV History [2.6] quoting “ ST is the world's leading manufacturer of analog ICs (integrated circuits) and MPEG-2 decoder chips, used to provide video decompression for DVD players and digital television set-top boxes.” and “Another area in which SGS Thomson became an early player was its development of MPEG decompression chips. The company's dedication to MPEG technology was risky, as a number of other digital video decompression schemes were competing for what promised to be a huge market in the future. SGS Thomson gained an early lead in the MPEG market, however, releasing its first Motion Estimation Processor in 1990. By 1993, the company had debuted its "multimedia" chip, capable of decompressing digital video files for display on a television set. This chip helped the company take a major position in the new set-top box market, starting with supplying the chip for the Hughes digital satellite television set-top box.” It helps to also state that ST was dominating the MPEG domain winning over the risks due to its early investments.<br />
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19) SGS-THOMSON was also not only pioneer of MPEG2 in satellite digital multimedia business with DirecTV but also in Cable business with Scientific Atlanta (which was acquired by Cisco later). Thanks to the collaboration the STi chips named 5600 and 5610 were the first chips to integrate graphics engine with multimedia processors [1.21], [1.22].<br />
|a6=One key initial obstacle was represented by the 2.0 and 1.2 um CMSO silicon technology that prevented to immediately super integrate in a single chip many other hardwired and micro controller bocks. Therefore, hardware designers had to carefully decide what to accelerate with respect to a software implementation, for example on 68020 micro controllers used in Apple computers or on ST8 micro controller. therefore as result of an accurate design, STV3200 needed only 115,000 transistors because of a deep hardware optimized design involving multiple technical dimensions such as. <br />
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1) data precision of internal calculations, as minimized between 8, 12 to 16 bits <br />
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2) datapath branches to compensate low precision compute of some parts of the low bit depth circuitry to be compliant with IEEE 1180-1990, the IEEE Standard Specifications for the Implementations of 8x8 Inverse Discrete Cosine Transform, <br />
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3) internal memory distribution, transposition [4.1][4.2] of read and write memory data access to avoid using costly additional SRAM blocks. <br />
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These dimensions were put in the chip despite the need to support various block formats such as 16x16, 8x8, 4x4, 16x8, 8x4, 8x16, 4x8 that will be specified many years later by MPEG-1,2, 4, H.264 and HEVC video standards. DCT coefficients were minimized to use only 12bits reducing furthermore internal memory footprint [4.6]. Internal data have been processed at 16 bits to minimize loss of precision instead of using 32 bits integer arithmetic. floating points was not considered as too transistor and silicon area demanding. Integrated memory was only 4Kbits and be transposable in the usage [4.1] [4.2] in real time by the internal controller avoiding unnecessary duplications and pipelining. Also, DCT mathematical separability to 1D was exploited to save silicon resources [4.7], [4.8], [4.9].<br />
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Similar optimizations were applied to STi3220 motion estimator based on block matching between block of pixels; by limiting the search window to 256 positions the silicon complexity of the block matcher was reduced, shifting the random-access memory bottleneck into proper pixel burst access to avoid the costly penalties of opening and closing memory pages (to access frame buffers) at pixel level with associated deadly loss of efficiency of the processor. Further innovative algorithms and hw design to achieve independence from the block based search windows estimation, therefore reducing computational complexity and be able to accurately estimate real life motion [1.27] [1.28]. Cache based motion estimation was introduced due to the recursive algorithms we invented and was designed to avoid block based data fetching with highly on chip data reusability therefore reducing memory bandwidth. [4.12] [4.13]<br />
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The software computing obstacle (and bottleneck) had to be addressed in the most efficient manner.<br />
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1) By hardwiring DCT and motion estimation/compensation processing functions, the most silicon area demanding function, hundreds of powerful micro controllers (such as Motorola 68020 or equivalent) were not anymore needed, while only an external 8bit controller using only 8Kbytes of ROM was capable to initiate decoding and searching operations once for any picture that was under decompression without being on the decoding critical path nor performing pixel level operations. That removed the need for any time critical handshake between the external micro controller and the integrated circuits, avoiding hardware pipeline stalls that could result in picture freeze or annoying block artefacts affecting picture quality.<br />
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Another challenge, as the silicon technology advanced for STi3240, STi3400, STi3500, STi3520, STi7000, STi5500 and successive derivative chips, was the memory bottleneck that became even more urgent to address due to the unified addressing space used by different accelerators. DRAM was costly, power hungry and severely limited in storage space and bandwidth which in turn prevented the super integration since required to store I, P, B pictures and MPEG compressed bitstream. Decoding PAL and NTSC resolutions into only 16 Mbits of memory, to keep low the costs, implied several tricks to be implemented such as MPEG-2 B pictures decoding on the fly [4.4] and frame buffer on the fly compression [4.3] [4.5] [1.11] applied to both standard and high-definition decoders across the STi family. Novel memory reductions technique fixed the obstacle allowing MPEG SD decoding in only 8Mbits and HTDV in 32Mbits one of the most impressive achievement at that time. The memory bottleneck was solved. In figure 9 the picture of the first consumer high definition MPEG video chip. The Motion compensation unit with memory reduction is the block on the bottom right corner, with a raw of memory at the bottom and two almost parallel rows on the top. These are mostly due to memory related to data management for decompression <br />
<br />
[[image:Figure12hdmpeg.GIF|thumb|Figure 9 STi7000 layout with memory reduction integrated]]<br />
<br />
The energy consumption obstacle needed to be addressed to avoid power hungry systems. SoC optimizations allowed to keep the power consumption challenge between 0.5 and 1 W because higher power consumption would have reduced dramatically the reliability of the chips which were not using any heat sink other than a cheap plastic package. This allowed to increase speed and functionality up to full High-Definition pictures within a single chip, also addressing the engine orchestrating obstacle due the on-chip CPU, video, audio and graphics concurrent executions and later on, super integrating also the micro controller (8 to 32bits), which resulted into dramatically minimized costs and greatly improved performances, as compared with competition multi-chip implementations.<br />
<br />
The STi family initially consisted of: STV3200 (DCT), STV3220 (Motion Estimator), STi3240, STi3400 (MPEG 1 video decoder), STi3500 (MPEG2 Video decoder), STi3520 (MPEG 2 audio and video decoder) , STi5600, STi5610 (MPEG 2 audio/video decoder with integrated powerful 2D graphics) and STi7000 (HD MPEG 2 video decoder and HD Display processor), STi5000 (integrating micro controllers) and many many others which we are not listing here for sake of brevity since spanning 30 years of developments.<br />
<br />
Using low pin count and plastic packages without heat sinks mitigated the manufacturing cost obstacle and increased reliability of those chips that also necessitated from a simple 8-bit micro controller to a more complex 32bits CPU as companion first and then integrated in the SoC. <br />
<br />
In term of addressing the acceleration obstacle, by using such a deep hardware optimized design approach vs a full software one, the achieved performances were incomparable to state of art micro controllers such as 68020 which was unthinkable to be used due the excessive two digits number of them (to implement the decoding function) since 68020 was not optimized to process 60 or 120 million of pixels per second such the one required by high-definition MPEG 2 decoding. This need was further exacerbated later by the need to use on screen graphics to enhance used experience.<br />
<br />
Another obstacle to address was user experience which required high quality images produced with real time graphics processing. This was addressed by super integrating incrementally powerful image blitters, on screen display processor, 3D and 2D vector graphics engines to support user interfaces, internet browsers, gaming and 3D TV. ST was the 1st in bringing 3D graphics to the digital consumer market by implementing OpenGL-ES and OpenVG standards from the Khronos group.<br />
<br />
[[image:Figura9 graphics.png|thumb|Figure 10 graphic images rendered by STi family to enhance user experience]]<br />
<br />
Organizational obstacles<br />
<br />
At the beginning in 1986 the digital multimedia applications and services were not existing because of the analog TV transmissions were dominating in everyone entertainment life, while the PC one was marginal for that domain. By consequence, the SGS-THOMSON management was reluctant to invest initially in a full generation of STi chips with an unpredictable return on investment a-head. The internal investments were purely R&D without any revenues, just losses in term of money discouraging further investments. The seminal cooperation between Rennes Electronics Laboratory, ENST Paris and Thomson Semiconductor under DAII sponsorship since 1986 first, then the development opportunities with Apple computer and RCA/DirecTV removed those barriers and were instrumental for SGS-Thomson to put 30 years of efforts into a roadmap of chips, manufacture them and to boost the chip production motivating subsequent investments and multimedia applications and service flourishment.<br />
<br />
The architecture of the DCT chip was invented at ENST, [4.10] [4.11] [7.0], and the DCT industrial chip that was designed within the ENST laboratory (Alain Artieri, a key ST architect, inventor and design engineer of the STi family spent a year in ENST team) using a specific CAD tool that was also developed within ENST, that made possible to generate this Hardware-Optimized solution. At that time, the head of the IC research group at ENST was Professor Francis Jutand, and Nicolas Demassieux was assistant professor. Nicolas Demassieux was personally participating to the MPEG1 (and later MPEG2) standardization efforts, and this work was fueled by EC-funded projects (such as the VADIS project). Both of Jutand and Demassieux, with Alain Artieri came to SGS-Thomson, to convince the company managers to adopt DCT architecture and CAD tool. At that time, the internal ST design team was proposing 12 chips solutions, using gate-arrays. It took nearly a year to convince the manager of ST design team that Jutand and Demassieux had a credible solution, and a contract was signed between ENST and ST to a) licensing the intellectual property of two patents to ST, and 2) set-up a joint-design team that would design the DCT chip. Alain Artieri came for a year in the ENST team, and we designed together (with help of a couple of younger students) the layout of chip, while all the verifications (DRC, logical simulation....) were carried out in ST at Grenoble. Both Alain Artieri and Nicolas Demassieux designed the chip as equals in the collaboration.<br />
<br />
The ST team in Grenoble should be hailed for this adventure, and for being open-minded to change their "usual way of working" and accept this innovative idea of a joint academic/industry design team, to deliver this world's first STV3200 chip. This was a unique case (to our best knowledge) of an industrial chip being designed by a joint academic/industry team, through the collaboration between ENST and ST. Initial research work at ENST in 1986, described in [1.24]. [4.10] [4.11] patents granted to ENST in 1986 resulting from this research. Licensing and contractual agreement between ST and ENST during 1986 with final meeting to close the deal on Nov 12, 1986.<br />
<br />
Key top management directive (from Aldo Romano, top executive with almost 47 years of tireless entrepreneurial work in ST) was to seek the market interest on those chips and to start working with an initial customer: it was Apple Computer with whom SGS-Thomson specified the first MPEG1 ST3240 chip using available STV3200 implementing DCT. Secondly it was RCA, acquired by Thomson Consumer Electronics, was massively investing on Digital Satellite broadcast but its end-to-end system was lacking affordable decoding technologies. SGS-Thomson management decision was to take the risk on the decoder development without any commitment from RCA to buy those chips, with potential loss of development costs if the product would go in production too late. Thanks to the deep hard work of SGS-Thomson a key ST engineer such as Alain Artieri and his colleagues, it was released to RCA, one and half year ahead of C-Cube therefore being the first decoder being adopted into DirectTV digital multimedia broadcast. The business was granted by ST ! The business started to be self sustainable and went on for 30 years !<br />
|a5=As reported into [1.9] many solutions for image and compression ICs were existing in 1992 however SGS-Thomson started since 1986. The ST innovations, which have been outlined in this IEEE Milestone proposal and which have created and provided significantly advancements in the field of digital multimedia, can be concisely summarized as follows:<br />
<br />
1) The silicon development started on 1986 between Rennes Electronics Laboratory, ENST Paris and Thomson Semiconductor under DAII sponsorship a-head of anybody else<br />
<br />
2) The 1st chip for mass production for forward and inverse DCT was STV3200 in 1988.<br />
<br />
3) The 1st chip for mass production for motion estimator was STV3220 in 1989. search window independence was further achieved with [1.27] [1.28] which mitigated the memory bottleneck by introducing cache based estimation<br />
<br />
4) Their hardwired implementations replaced software solutions which needed hundreds of Motorola 68020 which were unable to achieve production and deployment into end user Set top boxes and digital TV.<br />
<br />
5) They incrementally implemented innovative techniques to reduce memory bandwidth such as block based efficient burst memory read and write, picture decoding on the fly, frame buffer on the fly compression to minimize external RAM needs and enable super integration of 1 bit transistor memory RAM cells in an on per requirement fashion.<br />
<br />
6) Gave the designer the freedom to use more advanced CMOS silicon lithography such as 0.5, 0.35um and successive in order to achieve super integration of more and more functionalities, to meet affordable mass production. the last one developed by ST was 25nm FDSOI offering low power high density integration capabilities<br />
<br />
7) Integrate more heterogeneous functions such as micro controller (8 bits, 32bits), audio decoding and 3D OpenGL-ES graphics<br />
<br />
8) System on Chip integration including faster processor cores (high instruction per cycles and frequency), caches (to handle code density and latency), memory controllers (for minimal latency communication with DDR), assisted by tool chains (with compilers adopted by a wide developer community) <br />
<br />
9) Addressing HDTV/UDTV decoding, Video encoding and content Transcoding in real time<br />
<br />
10) Super integrating MPEG2 transport processing capabilities using STM32 bit microprocessor.<br />
<br />
11) Low dissipation <1W (figure 11) and high throughput efficiency<br />
<br />
[[image:Figure10 power consumption.png|thumb|Figure 11 Power dissipation minimized by STi family under 1W ]]<br />
<br />
12) A continued investment on R&D and production started on 1986 till 2016 for 30 years of break-through products that shaped the digital multimedia domain (figure 12). <br />
<br />
13) STi3500 was the enabler of the first Digital TV broadcast ever, that was the key to the worldwide leadership of SGS-THOMSON in digital multimedia market.<br />
<br />
[[image:Figure11 mpeg.png|thumb|Figure 12]]<br />
|references=1. TECHNICAL ARTICLES, CONFERENCE PAPERS & BOOKS<br />
<br />
[1.1] A. Artieri, S. Kritter, F. Jutand and N. Demassieux, "A one chip VLSI for real time two-dimensional discrete cosine transform," 1988., IEEE International Symposium on Circuits and Systems, 1988, pp. 701-704 vol.1, doi: 10.1109/ISCAS.1988.15022.<br />
<br />
[1.2] STV3200 DISCRETE COSINE TRANSFORM (DCT) Datasheet<br />
<br />
[1.3] A. Artieri and F. Jutand, "A versatile and powerful chip for real-time motion estimation," International Conference on Acoustics, Speech, and Signal Processing, 1989, pp. 2453-2456 vol.4, doi: 10.1109/ICASSP.1989.266964.<br />
<br />
[1.4] STi3220 MOTION ESTIMATOR PROCESSOR Datasheet<br />
<br />
[1.5] APPLICATION NOTE STi3220 MOTION ESTIMATION PROCESSOR CODEC<br />
<br />
[1.6] STi3400 MPEG/H.261 VIDEO DECODER DATASHEET<br />
<br />
[1.7] STi3500 MPEG2 CCIR 601H.261 VIDEO DECODER DATASHEET<br />
<br />
[1.8] Image and Video Compression standards: algorithm and architectures, Bhaskaran, Vasudev, Konstantinides, Konstantinos, ISBN 978-1-4615-6199-6, 1995<br />
<br />
[1.9] K. Konstantinides and V. Bhaskaran, "Monolithic architectures for image processing and compression," in IEEE Computer Graphics and Applications, vol. 12, no. 6, pp. 75-86, Nov. 1992, doi: 10.1109/38.163627.<br />
<br />
[1.10] A. Artieri and O. Colavin, "A chip set core for image compression," in IEEE Transactions on Consumer Electronics, vol. 36, no. 3, pp. 395-402, Aug. 1990, doi: 10.1109/30.103150.<br />
<br />
[1.11] A. Chimienti, M. Lucenteforte, D. Pau and R. Sannino, "A novel co-decoding scheme to reduce memory in MPEG-2 MP@ML decoder," 1998 URSI International Symposium on Signals, Systems, and Electronics. Conference Proceedings (Cat. No.98EX167), 1998, pp. 272-277, doi: 10.1109/ISSSE.1998.738080.<br />
<br />
[1.12] STi70000 press release<br />
<br />
[1.13] STi71000 datasheet<br />
<br />
[1.14] STi7200 datasheet<br />
<br />
[1.15] STi7108 datasheet<br />
<br />
[1.16] STi7108 processor with 3D graphics made public.<br />
<br />
[1.17] A chip set for MPEG-2 video encoding; Proceedings of the IEEE 1995 Custom Integrated Circuits Conference, 1995 <br />
<br />
[1.18] STi3240 MPEG1/H261 datasheet<br />
<br />
[1.19] STi3208 DCT chip datasheet<br />
<br />
[1.20] STi3520A MPEG2 chip datasheet<br />
<br />
[1.21] STi5600 MPEG2 chip datasheet<br />
<br />
[1.22] STi5610 MPEG2 chip datasheet<br />
<br />
[1.23] R. Bruni, A. Chimienti, M. Lucenteforte, D. Pau and R. Sannino, "A novel adaptive vector quantization method for memory reduction in MPEG-2 HDTV decoders," in IEEE Transactions on Consumer Electronics, vol. 44, no. 3, pp. 537-544, Aug. 1998, doi: 10.1109/30.713161.<br />
<br />
[1.24] F. Jutand, N. Demassieux, G. Concordel, J. Guichard and E. Cassimatis, "A single chip video rate 16×16 discrete cosine transform," ICASSP '86. IEEE International Conference on Acoustics, Speech, and Signal Processing, 1986, pp. 805-808, doi: 10.1109/ICASSP.1986.1169147.<br />
<br />
[1.25] N. Demassieux, G. Concordel, J. Durandeau and F. Jutand, "An optimized VLSI architecture for a multiformat discrete cosine transform," ICASSP '87. IEEE International Conference on Acoustics, Speech, and Signal Processing, 1987, pp. 547-550, doi: 10.1109/ICASSP.1987.1169851.<br />
<br />
[1.26] Tomasko, M., Buchhauser, D., Bushroe, M. et al. The Descent Imager/Spectral Radiometer (DISR) Experiment on the Huygens Entry Probe of Titan. Space Science Reviews 104, 469–551 (2002). https://doi.org/10.1023/A:1023632422098<br />
<br />
[1.27] An innovative, high quality and search window independent motion estimation algorithm and architecture for MPEG-2 encoding; FS Rovati, D Pau, E Piccinelli, L Pezzoni, JM Bard<br />
IEEE transactions on consumer electronics 46 (3), 697-705<br />
<br />
[1.28] A complexity-bounded motion estimation algorithm<br />
A Chimienti, C Ferraris, D Pau<br />
IEEE Transactions on image processing 11 (4), 387-392<br />
<br />
<br />
2. ONLINE INFORMATION AND CITATIONS<br />
<br />
[2.1] https://en.wikipedia.org/wiki/Motorola_68020 <br />
<br />
[2.2] https://techmonitor.ai/technology/sgs_thomson_debuts_one_chip_hdtv_system <br />
<br />
[2.3] Leonardo Chiariglione awards https://leonardo.chiariglione.org/public-life/awards/ <br />
<br />
[2.4] see pdf and https://www.eetimes.com/apis-help-stmicroelectronics-grow-set-top-box-business/# <br />
<br />
[2.5] see pdf and https://www.edn.com/sgs-thomson-microelectronics-named-number-one-mpeg-decoder-supplier-by-dataquest/ <br />
<br />
[2.6] see pdf and http://www.fundinguniverse.com/company-histories/stmicroelectronics-nv-history/ <br />
<br />
[2.7] https://books.google.it/books?id=C-bgBwAAQBAJ&pg=PA234&lpg=PA234&dq=stv3200+sgs-thomson&source=bl&ots=HrOQA0LEvS&sig=ACfU3U0vpZ7K5HJzJ1qJWjjlk4yfzPW82w&hl=it&sa=X&ved=2ahUKEwj2lZ2p35HwAhWBzKQKHVrmBBMQ6AEwEnoECBUQAw#v=onepage&q=stv3200%20sgs-thomson&f=false <br />
<br />
[2.8] http://www.quretec.com/u/vilo/edu/2002-03/Tekstialgoritmid_I/Loengud/Loeng7_Compression/www.faqs.org/faqs/compression-faq/part1/preamble.html<br />
<br />
[2.9] https://books.google.fr/books?id=UsH8CAAAQBAJ&lpg=PA501&ots=OJr_PN0LKo&dq=stv3200%20DCT&hl=fr&pg=PA501#v=onepage&q=stv3200%20DCT&f=false <br />
<br />
[2.10] http://ciclops.org/ir_index/208/In-Orbit?js=1 <br />
<br />
<br />
3. STMicroelectronics documents<br />
<br />
[3.1] De la Transformée en Cosinus Discrète aux Processeurs Applicatifs Multimédia, Alain Artiéri, Septembre 2007, STMicroelectronics presentation<br />
<br />
4. PATENTS<br />
<br />
[4.1] Integrated signal processing circuit for online and column summation of digital value matrices https://patents.google.com/patent/FR2608802B1/en?inventor=alain+artieri&oq=alain+artieri&sort=old <br />
<br />
[4.2] Transposition memory for data processing circuit https://patents.google.com/patent/FR2617621B1/en?inventor=alain+artieri&oq=alain+artieri&sort=old <br />
<br />
[4.3] Method and apparatus for addressing a memory area of an MPEG decoder4.6<br />
<br />
[4.4] publication number US6081298A MPEG decoder with reduced memory capacity<br />
<br />
[4.5] ITVA960016D0 Metodo di ricompressione e decompressione adpcm di un flusso di dati digitali costituente un segnale video digitale e stimatore https://patents.google.com/patent/ITVA960016D0/it?inventor=danilo+pau&oq=danilo+pau&sort=old<br />
<br />
[4.6] publication number 0 298 002 of 29.06.1988 Memoire de transposition pour circuit de traitement de donnes<br />
<br />
[4.7] publication number FR2649226A1 BREWING CIRCUIT OF DATA<br />
<br />
[4.8] publication number FR2650462B1 Device for converting a line scanning into a scanning in vertical saw teeth by bands; https://patents.google.com/patent/FR2650462B1/en?q=H04N3%2f30&inventor=alain+artieri&sort=old <br />
<br />
[4.9] publication number EP0368731B1 Process and circuit for image representation signal filtration<br />
<br />
[4.10] Circuit pour effectuer une transformation linéaire sur un signal numérique Patent issuer and number eu EP 0241352 A1 https://patents.google.com/patent/EP0241352A1<br />
<br />
[4.11] Additionneur binaire comportant un opérande fixé, et multiplieur binaire parallèle-série comprenant un tel additionneur Patent issuer and number eu EP 0262032 B1 https://patents.google.com/patent/EP0262032B1<br />
<br />
[4.12] VLSI architecture, in particular for motion estimation applications<br />
F Rovati, D Pau, L Fanucci, S Saponara, A Cenciotti, D Alfonso<br />
US Patent 6,724,823<br />
<br />
[4.13] Motion estimation process and system<br />
D Pau, E Piccinelli, F Rovati<br />
US Patent 6,891,891 <br />
<br />
5. Honors<br />
<br />
[5.1] Two European IT Prizes Awarded to STMicroelectronics<br />
<br />
6. MPEG mentions<br />
<br />
[6.1] Chiariglione and the birth of MPEG https://www.chiariglione.org/public-life/media/leonardo_ieee/prof.htm <br />
<br />
7. Letters of support<br />
<br />
[7.0] Endorsement by Nicolas Demassieux, Senior Vice President of<br />
Research, Orange, assistant professor at ENST (now Telecom ParisTech) mid 80s.<br />
<br />
[7.1] Endorsement by Leonardo Chiariglione, PhD Eng, the father of MPEG<br />
<br />
[7.2] Endorsement by Professor Emeritus Fabio Rocca, Politecnico di Milano, pioneer of motion estimation in 1969<br />
<br />
[7.3] Endorsement by Hisafumi Yamada, former Sony US TV CTO<br />
<br />
[7.4] Endorsement by Sylvain Kritter, Product Director VIZYON<br />
<br />
[7.5] Endorsement by Professor Emeritus Virginio Cantoni, University of Pavia. Also Fellow of the IAPR since 1994 and Life Fellow of the IEEE (he was Fellow since 1997). In 2006 the President of the Italian Republic conferred to Professor Virginio Cantoni the title of ‘Commander of the Order of Merit of the Italian Republic’.<br />
<br />
[7.6] Endorsement by Professor Emeritus Mariagiovanna Sami, Politecnico di Miano. Past Full Professor, Digital Systems. IEEE Life Member. Minerva prize for woman scientists, the Seymour Cray prize for contributions in the area of parallel processing, the Herbert A. Simon Gold Medal, assigned by the Society for Design and Process Science. Cavaliere della Repubblica Italiana (knight of the Italian republic). Member of the Italian National Science Academy (“Dei Quaranta”).<br />
<br />
[7.7] Endorsement by Professor Andrea Basso who directly contributed to MPEG standards since 90s while in EPFL and in AT&T Bell labs and AT&T Research Laboratories, Middletown, NJ, USA<br />
|submitted=Yes<br />
}}</div>Administrator1http://ieeemilestones.ethw.org/index.php?title=Milestone-Proposal:SGS-THOMSON_MPEG_integrated_circuits&diff=11112Milestone-Proposal:SGS-THOMSON MPEG integrated circuits2021-06-03T18:43:08Z<p>Administrator1: Administrator1 moved page Milestone-Proposal:SGS-THOMSON MPEG integrated circuits to Milestone-Proposal:MPEG integrated circuits</p>
<hr />
<div>#REDIRECT [[Milestone-Proposal:MPEG integrated circuits]]</div>Administrator1http://ieeemilestones.ethw.org/index.php?title=Milestone-Proposal:MPEG_integrated_circuits&diff=11026Milestone-Proposal:MPEG integrated circuits2021-05-12T15:34:24Z<p>Administrator1: </p>
<hr />
<div>{{Proposal<br />
|litigation=No<br />
|more than 25 years=Yes<br />
|within fields of interest=Yes<br />
|benefit to humanity=Yes<br />
|regional importance=Yes<br />
|ou is paying=Yes<br />
|ou is arranging dedication=Yes<br />
|section is taking responsibility for plaque=Yes<br />
|a11=Yes<br />
|a3=1986<br />
|a1=Multimedia Integrated Circuits for MPEG, 1986<br />
|plaque citation=SGS-THOMSON (now STMicroelectronics) pioneered the family of multimedia integrated circuits, accelerating Moving Picture Experts Group (MPEG) standards. Discrete Cosine Transform designed with ENST (now Telecom ParisTech) was the first. Innovative memory reduction techniques, highly optimized dedicated hardware accelerators, super-integration of heterogeneous processor units achieved significant performances and cost reduction with minimized energy consumption. These integrated circuits were the key enabler of digital multimedia services to entertain end-users in everyday life.<br />
|a2b=France Section<br />
|IEEE units paying={{IEEE Organizational Unit Paying<br />
|Unit=France<br />
|Senior officer name=Claire LAJOIE-MAZENC<br />
|Senior officer email=claire.lajoie-mazenc@rte-france.com<br />
}}<br />
|IEEE units arranging={{IEEE Organizational Unit Arranging<br />
|Unit=France with STMicroelectronics<br />
|Senior officer name=Claire LAJOIE-MAZENC<br />
|Senior officer email=claire.lajoie-mazenc@rte-france.com<br />
}}<br />
|IEEE sections monitoring={{IEEE Section Monitoring<br />
|Section=France<br />
|Section chair name=Claire LAJOIE-MAZENC<br />
|Section chair email=claire.lajoie-mazenc@rte-france.com<br />
}}<br />
|Milestone proposers={{Milestone proposer<br />
|Proposer name=Danilo Pau<br />
|Proposer email=danilo.pau@st.com<br />
}}{{Milestone proposer<br />
|Proposer name=Jean-Michel Moutin<br />
|Proposer email=jean-michel.moutin@st.com<br />
}}<br />
|a2a=(45.203333, 5.695833)<br />
|a7=The Grenoble site is of premier importance for STMicroelectronics since was owned by THOMSON SEMICONDUCTEURS and then merged with SGS in 1987 to form SGS-Thomson (now STMicroelectronics). Nowadays is the biggest R&D site of STMicroelectronics, hosting many product divisions from the three Product Groups of the company, including silicon and software design, test, and advanced packaging developments. The site were MPEG chips were conceived and designed<br />
|a8=Yes, even if part of them were restructured they still exists @ STMicroelectronics, 12, rue Jules Horowitz F-38000 Grenoble, France<br />
|mounting details=Plaques will be installed in a public place at the main entrance as shown below. It will be close to ST security personnel who are is monitoring entrance 24 hours in a day, every day in a year. Very close as indicated there are other public roads. Plaque will be placed at 12, rue Jules Horowitz F-38000 Grenoble, France. GPS coordinates are: 45°12’12” N ; 05°41’45” E (45.203333, 5.695833). Therefore, visitors will not need to be escorted by ST guards to look the plaque or to take a snapshot of it. The milestone plaque will be installed right in front of STMicroelectronics, main entrance access. It is where employees, visitors and customers must pass to get into the ST Grenoble offices on daily basis. It is monitored continuously 24h/7d by ST security human resources and surveillance camera. It is a public place, right outside ST site restricted perimeter.<br />
|a9=It is protected by ST security human resources and with surveillance camera, 24h/7d. It is publicly and easily accessible from 12, rue Jules Horowitz F-38000 Grenoble, France. The site can be reached also from Lion Airport, close to Grenoble as shown in figure 2.<br />
|a10=STMicroelectronics (Grenoble 2) SAS<br />
|a4=[[image:Figure1 Placque installation.jpg|thumb|Figure 1]]<br />
<br />
[[image:Figure2 map to grenoble.jpg|thumb|Figure 2]]<br />
<br />
The technology objective of STMicroelectronics was to conceive, ahead of MPEG standard, and introduce innovative hardware solutions able to achieve several order of magnitude speed acceleration, compared to unfeasible full software implementation of MPEG decoding and encoding functionalities, by introducing for the first time memory compressions and reductions, dedicated hardware implementation in order to save silicon area per technology node, super integrate new functionalities in a less than a watt power envelope. <br />
The DCT circuit, the first in the family, was so reliably designed and produced that was subsequently used in the Cassini-Huygens probe for transmitting compressed images of Saturn during 20 years.<br />
<br />
Specific objectives, that motivated STMicroelectronics (short name ST) to pioneer Mpeg family of System on a Chips and associated CMOS silicon technology development to implement it and starting since 1987 and onward, were:<br />
<br />
1) To create reliable and low complex CMOS building (integrated circuits) blocks at production maturity to dramatically accelerate real time MPEG video decoding and encoding functionalities at increasing image resolutions and frame rates.<br />
<br />
2) To super-integrate such building blocks in more complex integrated circuits and SoCs to accelerate MPEG 1, 2, 4, H264, HEVC and subsequent standardized specifications, at the same time they were under development. In other words before the standards were officially frozen and went public.<br />
<br />
3) To achieve lowest on chip memory footprint and bit-depth of computing data paths to dramatically save silicon area given the existing (µm) CMOS technology constraints for mass production and reliable manufacturability with marginal chip defectivity.<br />
<br />
4) To achieve minimal power consumption, to and below 1W across different silicon technologies generations and starting from 1.2um silicon gate manufacturing processes. Successive lower dimension lithography, were needed considering an increasing need to super integrate functionalities, heterogeneous hardware accelerators, microprocessors, graphic engines, crypto engines, a rich set of peripherals and interfaces etc.<br />
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5) To remove any need of costly and bulky heat-sinks as well as complex cooling mechanisms to offer an easier viable integration into thinner video equipment manufactured systems.<br />
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6) To dramatically reduce as low as possible video communication bandwidth between the chip and the external DRAM memories to minimize memory requirements of those chips and associated costly power consumption.<br />
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7) To control those chips with very simple and low computing power 8bits micro controllers and incrementally as requirements will grew with 32 bits: this to support flexibility that requires further software computing needs to offer un precedented user experience. Including the use of advanced graphics to ease content accessibility and fruition.<br />
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8) To enable viable, widely adopted, broad range of diversified digital multimedia applications and services, implying affordable software development and deployment to a vast range of end users at worldwide level with different needs.<br />
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In the following there is the summary of achievements by STi family in the present milestone proposal. To meet the above-mentioned challenging objectives and long-term technology vision, ST, since 1986, has developed following key technologies and chips. A few but very relevant technologies and chips will be described, because the family is too huge to report completely in this document.<br />
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1) Seminal work on ST CMOS technologies, started at ENST [1.24] [1.25] [7.0] with Thomson Semiconductors (now STMicroelectronics), produced the architecture of an economically reasonable chip implementing various sizes DCT 16x16, 16x8, 8x8, 8x4, 4x4. The main features of the chip under development with THOMSON SEMICONDUCTEURS in 2 µm first and then 1.25 µm CMOS technology were 70,400 Transistors, 25 mm2, Internal clock 13.5 MHz, Direct/Reverse DCT, 8 bits pixels, 16 bits internal accuracy. The chip was sampled by THOMSON SEMICONDUCTEUR in October 1987.<br />
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2) STV3200 [1.1] [1.2] was a dedicated integrated circuit to accelerate the discrete cosine transform (DCT). The two-dimensional forward DCT (FDCT) and inverse DCT (IDCT) was implemented for various image block sizes and the pixel rate was up to 15.0 MHz The circuit architecture was fully bidirectional with a 9-bit magnitude pixel data bus and a 12-bit magnitude coefficient data bus programmed as input or output depending on the selection of Forward DCT or Inverse DCT function. DCT was so complex that to be implemented on a CPU required about 1 billion additions per second (1 giga Hertz operations per second) to process the moving pictures in real time. CPUs and CMOS silicon process were unable to achieve such a very high frequency, therefore implying the computing power of fifty Motorola 68020 [2.1], one of the faster micro-processors in the 1980s. The integrated circuit went officially in production at the end of 1987 and was a world premiere product. Since 1988, this component was successfully sold by SGS-Thomson. It implemented key patents [4.1][4.2] for rearranging, permuting or selecting data according to predetermined rules, for changing the order of data flow, e.g. matrix transposition, LIFO buffers; Overflow or underflow handling that were key for DCT and IDCT implementations.<br />
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Innovative memory footprint reduction and distribution techniques were used since the hardware design did not use the traditional architecture (such as a unique multiplier that would read/write in a large memory), but a bit-serial pipelined architecture, where memory was distributed across the chip, to feed the 16 bit/serial dedicated multipliers that the chip had.<br />
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The STV3200 chip was used in the DISR (descent imager) [1.26] [2.9] [7.0] of Cassini-Huygens probe that was launched in 1997 and has transmitted magnificent images of Saturn until 2017. All the wonderful images that are available in this site [2.10] have been processed through the chip!<br />
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Design of the STV3200 happened during the December 1986 to August 1987 period (product sampling around October 1987) as mentioned at the end of [1.25]. As said commercialization of the STV3200 started in 1988 while on November 1988 there was the publication of the H261 standard (1st standard using DCT for real time video coding) and on May 1988 there was the 1st meeting of the MPEG standard (that was published in 1993).<br />
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[[image:Figure3 dct chip.jpg|thumb|Figure 3 DCT chip]]<br />
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3) STi3220 [1.3] [1.4] [1.5] was the second member of the family, a real time motion estimation integrated chip dedicated to motion estimation at video rates. The chip was optimized to compute the displacement vector of 8x4n or 16x4n pixel blocks in a search window, between temporally distant pictures, defined by a maximum horizontal and vertical displacement of +7/-8 pixels corresponding to 256 different vectors. The chip computed 256 distortion for each block according to the MAE (mean absolute error) criteria. The motion estimation required about 4 billion of additions per second (4 giga Hertz operations per second). If it would be implemented on CPU it would require the equivalent computing power of several hundred of Motorola 68020. Therefore, it was unfeasible in software. Its development started in 1988, went in production and be sold by SGS-Thomson since 1989. This component was another world premiere product in conjunction with STV3200. Furthermore, the Motion estimation processor was a key building block to accelerate more complex MPEG-2 Video Encoders [1.17]<br />
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4) Super integration of those fundamental functions with others fundamental building blocks (e.g. scalar quantization and de-quantization, entropy coding and decoding, motion compensation, unified memory management), was the next vital step required to manufacture reliable system solution for mass production while before they were consisting of few chips. In this respect [1.20] presents the deployment of STV3200 and STi3220 in a complete video codec hardware architecture for high pixel rates addressing standard (SD) and high definition (HD) picture formats.<br />
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5) STi3240 [1.18] was the 1st MPEG1/H261 chip with STV3208 (DCT processor) [1.19] supporting video decoding schemes up to 10 Mbit/s of the ISO/MPEG future (at that time under active definition) video standard and CCITT/H261 recommendation at video rate (352x288 pixels at 30fps). It required between 512 KBytes up to 4Mbytes of external DRAM with a 8/16 bits microprocessor interface. External DRAM was a scarce and costly resource, dramatically impacting the overall power consumption and bill of material. Therefore, the use of memory reduction techniques to support high chip calculations throughput and minimized data bandwidth between the chip and the memory were conceived for the first time and implemented.<br />
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[[image:Figure4 decoder figure.png|thumb|Figure 4 decoder system, STV3208 was DCT co processor]]<br />
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6) Then the super integration of way started with active development of System of Chip. Earliest members of the STi digital multimedia chip family for mpeg moving picture processing were: STi3400, STi3500, STi3520A. Other early examples were STi7000, STi5000 (and the very many others that followed). They were the first able to offer a dramatic reduction in silicon and package size, power consumption, with higher level of transistors integration, functionalities, and lowest cost of equipment’s. Such equipment’s were made previously by many un-optimized discrete signal processors (DSP) and which were placed into many more boards. They far from being manufacturable viably and affordably for MPEG-1 and MPEG-2 standards deployment at end user side. STi chips were very instrumental to accelerate the introduction to the end users of CD-ROM, DVDs, Set Top Box and digital TVs that became ubiquitously adopted throughout the entertainment world and in everyone home (and mobile phones) across 3 decades.<br />
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7) Inside those chips’, innovative and advanced reduction techniques of external memory bandwidth were conceived and implemented first. They were key to lower power consumption to and under 1W. In that respect several key methods are described in the following subsections:<br />
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a) block based pixel memory addressing and communication [4.3] allowed to minimize the cost of external memory page openings and closures, distributing the costly overhead per block size (composed by several pixels) instead of per single or per few pixels. In turn this allowed to avoid hardware pipeline stalls resulting in using peak performances and resulting in a full motion interactive frame rates, clear picture decoding, free from block artefacts<br />
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b) picture decoding on the fly [4.4] was a break-through technology to decompress and motion compensate at the same time while displaying MPEG B-pictures. This to avoid inefficient and further storage of them in the external frame buffer, thus resulting in a dramatic reduction of the external memory to only 16 Mbits for SD definition [1.20]<br />
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c) frame buffer compression [1.11] [4.5] was another key technology used to co-decompress on the fly I , P and B MPEG pictures by halving the associated external DRAM memory and the memory bandwidth without annoying picture artefacts. Indeed, in STi solution the quantization noise was cleverly masked by MPEG coding noise, resulting in not human perceivable loss of quality. This allowed to reach 8 Mbits DRAM footprint in SD enabling super integration of 1 bit transistor per cell DRAM on the same chip, in a more competitive way than integrating 6 transistor per cell SRAM. Since then STi did not require any additional external memory for the MPEG SD video decompression task. Another kind of memory reduction was applied to HDTV decoders with even further benefits. [1.23] was novel method to reduce the external memory needed by STi MPEG-2 HDTV decoder architecture. The total amount of memory was reduced from 96 to 32 Mbits preserving a good picture quality. Furthermore, it required low hardware complexity increases of less than 5%, in 0.35 pm technology, the total decoder silicon area with respect to the standard decoder.<br />
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8) The STi implementation of the ST comprehensive vision to create the digital Multimedia domain was made possible with those and many other chips. <br />
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However, the pioneering development work began since 1986 [1.24] [1.26] among different and key French partners:<br />
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1) Thomson Semiconductor (merged later into SGS-THOMSON, now STMicroelectronics) launched innovative circuit architecture studies for integrated for the Discrete Cosine Transform since 1986<br />
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2) ENST Paris (now Telecon ParisTech) was very active and interested since 1986 in integrated circuit architectures for DCT [1.24] [1.25] single chip for video rates.<br />
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3) Rennes Electronics Laboratory, expert in the field of image compression, built image transmission equipment between studios and digital recording.<br />
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Under the finance support of the DAII (French State Agency) these three laboratories collaborated to form a team responsible for realizing the first DCT component (STV3200) and the Motion Estimation chip (STi3220). The DCT and Motion estimation chips existed thanks to the strong collaboration between SGS-Thomson and the public research lab of ENST.<br />
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Thus, on 1988, SGS-THOMSON finalized these seminal developments in production (but with background developments since 1986 [1.24] [1.26] in Thomson Semiconductor) therefore creating the wave of key circuits and SoC for MPEG. By consequence it mastered at industrial level initially the 2 key components which made possible and economically viable the realization of more complex, reliable, ready for mass production, yet low cost and low power MPEG-1 and MPEG-2 encoders and decoder systems for the (mid 80s) for the not existing digital multimedia television markets. <br />
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9) Apple Computer was looking for a technology partner in the field of image compression. Since aware of above-mentioned developments, contacted SGS-THOMSON in 1988. The 68020 microprocessors was used from March 1987 to March 1992 and only used twice, once in the Macintosh II as a high-end processor, and then again with the Macintosh LC, as a low-end processor. However, it was too slow and inadequate to support video decoding functions as for MPEG decoding. From this key technical limit, a collaboration with SGS-Thomson was started, the first in its kind, to study and develop highly integrated set of components to provide video functions for Apple's microcomputers. That was a very advanced concept for that time. <br />
Therefore SGS-THOMSON entered a partnership with Apple. Thus, based on SGS-THOMSON understanding of 68020 limits and the contribution of innovative chip solutions from SGS-THOMSON, the first architecture of an integrated system for image compression was defined to support the MPEG1 standard: the STi3240 [1.18], STi3400 [1.6]. STi3400 was a real time video, super integrated with DCT, decompression integrated processor supporting MPEG-1 and H.261 standards. The digital output was for PAL 50Hz and NTSC 60 Hz interlaced displays.<br />
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10) Next leveraging his expertise, SGS-THOMSON started a background work with RCA, which ended in 1992 with the development of an MPEG2 video decoder, STi3500 [1.7] and subsequent STi3520 [1.8]. Those were other essential components at the heart of the revolutionary multimedia digital television services introduced firstly from the USA Digital Satellite DirectTV firm. SGS-THOMSON succeeded in delivering the first MPEG2 decoder in the world, much ahead of the Californian start-up C-CUBE. It must be noticed that C-Cube was funded on 1988 when SGS-THOMSON had already above-mentioned chips in production and when Thomson semiconductor started on 1986. <br />
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11) STi3500 was a real time video decompression integrated circuit supporting MPEG-1 and MPEG-2 standards at video rates up to 720x480x60Hz or 720x576x50Hz requiring minimal support from an external 8bit microcontroller (ST8) used only to initialize the chip, reducing the complexity of software and associated code footprint. It required only 1W of power consumption. The STi3500 was a success since achieved a turnover greater than $ 100M in less than 3 years as a sign of market adoption. In that chip STV3200 (which was super integrated) represented only 10% of the total silicon area. STi3520 on top of STi3500, used only 16Mbits memory and integrated audio decoder compliant with MPEG layers I and II supporting sampling rates of 32, 44.1 and 48 KHz. STI3520A [1.20] was a single chip for MPEG MP@ML video decoding in only 16 Mbit RAM integrated with STi4500 MPEG L1 and L2 Audio decoder and integrating on screen display generator. The chip was using 0.5µm CMOS SGS-THOMSON technology<br />
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12) STi7000 [1.12] [2.2] was an integrated system for High-Definition Television (HDTV), which combined an MPEG-2 decoder with a display and format converter onto one chip in 1998. As already introduced in point 5) the most advanced trick was the frame buffer memory reduction through tiny on chip compression engine based on scalar adaptive quantization allowing full HDTV pictures to be decoded and displayed with only 64 Mbits of external memory instead of 128 Mbits. Designed for use in HDTV and other digital TV receivers, set top boxes and PCs, the STi7000 was developed in collaboration with Thomson Multimedia, a strategic partner with whom SGS-THOMSON shared a joint design center in Grenoble, France. The chip incorporated all the 18 video formats defined by the ATSC (Advanced Television Systems Committee) and Grand Alliance specifications. STi7000 supported video rates of up to 1920 x 1088 x 30Hz interlaced or 1280 x 720 x 60Hz progressive. Built in 0.35-micron SGS-Thomson HCMOS6 silicon technology, the STi7000 also included interfaces for a host microcontroller, local SDRAM, standard or high-definition video output and D1 digitized video input. Next versions STi7100 [1.13] STi7200 [1.14] also integrated graphics engine and power powerful micro controllers. STi7108 had dual ST40-300 CPU host processors linked to a 256K L2 cache giving up to 2000 DMIPS performance and a total of 4000 DMIPS. A 3D graphics engine [1.15] enabled advanced Internet content and high-performance gaming. It was the first set-top box IC [1.16] in the market to combine 3D OpenGL-ES 2.0 graphics, Ethernet, USB and e-SATA interfaces to connect Internet devices, DVR storage or external Flash or hard-disk (HDD) drives. <br />
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13) The STi5500 was the first member of back-end decoders for set-top boxes and DVD players. Compliant with MPEG-2 to decode its transport stream and convert it into sounds and images that sent to loudspeakers, monitors, TV screens and similar human interfaces. The STi5500 was the first integrated circuit in the world to incorporate not only all the circuitry required to handle all the back-end functions but also a 32-bit microprocessor. The built-in microprocessor had sufficient processing power to handle system-level functions as well as the managing the MPEG decoding function, so it eliminated the need for a separate system controller in most applications. Its super integration was the crucial factor and achieved immediate customers adoption. Since then, ST has developed even more powerful members including the STi5505, which is the first silicon chip in the world to integrate all the back-end functions of a DVD player. <br />
As demonstration of the innovation it brought in the field of digital multimedia, STi5500 won [5.1] from a field of nearly 300 nominations, the prestigious European IT PrizesPrize awarded by the European Commission in conjunction with Euro-CASE, the European Council of Applied Science and Engineering, for the development of products that are expected to play fundamental roles in helping European industry to increase its share of world markets.<br />
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Summarizing SGS-THOMSON STi gained its leadership position in the field of digital consumer multimedia decoder-type products for digital satellite TV and DVD players. Early members such as STV3200, STi3220, STi3240, STi3400, STi3500, STi3520A, STi7000, STi7100, STi7108, STi5500 SoC through the 80s, 90s and 2000 years continued for the development of digital multimedia applications at heart of the worldwide digital multimedia convergence of the TV services for everyday users, the world of telecommunications and the world of the PC. <br />
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Many other generations were manufactured across the years as shown in the next figure 5 even supporting complex operative systems such as Linux.<br />
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[[image:Figure5 chiproadmap.png|thumb|Figure 5]]<br />
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Interestingly many decades later, the pioneering work that conducted to STV3200 represented less than 0.1% of the surface of the SoC (figure 6). <br />
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[[image:Figure6 chip integration.jpg|thumb|Figure 6 Super integration of DCT with other multimedia functions]]<br />
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Until STMicroelectronics has sold over 500,000,000 (cumulated) of those integrated systems worldwide. This figure undoubtedly demonstrates the pervasive of STi family through the world. Figure 7 shows cumulative shipments of ST products per year basis.<br />
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[[image:Figure7 cumulative shipments.png|thumb|Figure 7]]<br />
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14) As proof of the high relevance of the proposed milestone a number of letter of supports were provided by key and well know experts in the field<br />
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a) A letter of endorsement [7.0] to ST milestone is provided by Nicolas Demassieux, Senior Vice President of Research, Orange [2.3], and assistant professor at ENST (now Telecom ParisTech) working on very optimized VLSI implementations for signal processing, included the DCT processor.<br />
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b) A letter of endorsement [7.1] to ST milestone is provided by Leonardo Chiariglione [2.3], the father of MPEG and the driving force behind MPEG standards for digitized video. Leonardo is unanimously considered a genius since created a new way of enjoying music, with Leonardo Chiariglione’ s MP3 standard.<br />
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As mentioned in the public article [6.1] with Leonardo Chiariglione, SGSThomson has been a big MPEG driver since it was the world's leading producer of MPEG-related ICs and supplied close to 70 percent of the world's MPEG-2 decoder chips. That was the result of the audiovisual vision that was shared by the leaders of SGS-Thomson, Thomson Multimedia SA, Paris, and France's government. Also, Chiariglione noted, Thomson's U.S. subsidiary RCA was in the need of MPEG chips for a huge order of 1st generation satellite TV decoders--a million set-top boxes for the Hughes-RCA DirecTV newborn system--and SGS-Thomson Microelectronics got the contract, as proof of its leading integrated circuits technology started since 1986.<br />
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c) A letter of endorsement [7.2] to ST milestone is provided by prof Fabio Rocca. Prof Rocca on 1969 was the pioneer on motion estimation and compensation technologies.<br />
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d) A letter of endorsement [7.3] to ST milestone is provided by Hisafumi Yamada, past Sony USA TV CTO that prove the high innovation STi HDTV chips provided to ATV USA television.<br />
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15) In the following years STi products on MPEG where the key enabling factor of a huge digital consumer ecosystem composed by many operators, equipment manufacturers, software developers and conditional access companies as shown in the next figure 6<br />
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[[image:Figure8 ecosystem.png|thumb|Figure 8 Worlds wide level ecosystem for digital multimedia services created thanks to STi family]]<br />
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16) As written in the EETimes article [2.4] “In the first shift or wave (referred to in the set-top box market) , which began about 1994, the boxes were simple channel-hopping devices for satellite and cable TV providers, Hatch explained. (ST's MPEG-2 video decoders were used then in the boxes manufactured by Thomson's RCA subsidiary.)” which clearly witness how ST was ahead.<br />
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17) As written in the EDN article [2.5] on 1996 “Dataquest has confirmed SGS-THOMSON Microelectronics (Lincoln, MA) as the world's leading supplier of MPEG decoder ICs in 1995.” which witnessed ST leadership on MPEG decoders.<br />
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18) as written into a public article STMicroelectronics NV History [2.6] quoting “ ST is the world's leading manufacturer of analog ICs (integrated circuits) and MPEG-2 decoder chips, used to provide video decompression for DVD players and digital television set-top boxes.” and “Another area in which SGS Thomson became an early player was its development of MPEG decompression chips. The company's dedication to MPEG technology was risky, as a number of other digital video decompression schemes were competing for what promised to be a huge market in the future. SGS Thomson gained an early lead in the MPEG market, however, releasing its first Motion Estimation Processor in 1990. By 1993, the company had debuted its "multimedia" chip, capable of decompressing digital video files for display on a television set. This chip helped the company take a major position in the new set-top box market, starting with supplying the chip for the Hughes digital satellite television set-top box.” It helps to also state that ST was dominating the MPEG domain winning over the risks due to its early investments.<br />
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19) SGS-THOMSON was also not only pioneer of MPEG2 in satellite digital multimedia business with DirecTV but also in Cable business with Scientific Atlanta (which was acquired by Cisco later). Thanks to the collaboration the STi chips named 5600 and 5610 were the first chips to integrate graphics engine with multimedia processors [1.21], [1.22].<br />
|a6=One key initial obstacle was represented by the initially used 1.2 um silicon technology that prevented to super integrate in a single chip too many hardwired and micro controller bocks. Therefore, hardware designers had to carefully decide what to accelerate with respect to a software implementation, for example on 68020 micro controllers used in Apple computers. In fact, STV3200 needed only 115,000 transistors because of a deep hardware optimized design involving multiple technical dimensions. <br />
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1) data precision of internal calculations, as minimized between 8, 12 to 16 bits <br />
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2) datapath branches to compensate low precision compute of some part of the low bit depth circuitry to be compliant with IEEE 1180-1990, the IEEE Standard Specifications for the Implementations of 8x8 Inverse Discrete Cosine Transform, <br />
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3) internal memory distribution, transposition [4.1][4.2] of read and write memory data access to avoid using costly additional SRAM blocks. <br />
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These dimensions were met in the chip despite the need to pioneer the support of various block formats such as 16x16, 8x8, 4x4, 16x8, 8x4, 8x16, 4x8 that will be used many years later by MPEG-1,2, 4, H.264 and HEVC video standards. DCT coefficients were minimized to use only 12bits reducing furthermore internal memory footprint [4.6]. Internal data have been processed at 16 bits to minimize loss of precision instead of using 32 bits integer arithmetic. Integrated memory was only 4Kbits and be transposed [4.1] [4.2] in real time by the internal controller avoiding unnecessary duplications. Also, DCT separability to 1D was exploited to save silicon resources [4.7], [4.8], [4.9].<br />
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Similar optimizations were applied to STi3220 motion estimator based on block matching between block of pixels; by limiting the search window to 256 positions the silicon complexity of the block matcher was reduced, shifting the random-access memory bottleneck into proper burst access to avoid the costly penalties of opening and closing memory pages (to access frame buffers) at pixel level with associated deadly loss of efficiency of the processor.<br />
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The software computing obstacle had to be addressed in the most efficient manner.<br />
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1) By hardwiring DCT and motion estimation/compensation processing functions, the most silicon area demanding function, hundreds of powerful micro controllers (such as Motorola 68020 or equivalent) were not anymore needed, while only an external 8bit controller using only 8Kbytes of ROM was capable to initiate decoding and searching operation once any picture was under decompression without being on the decoding critical path nor perform pixel level operations. That removed the need for any handshake between the external micro controller and the integrated circuits, avoiding hardware pipeline stalls that could result in picture freeze or annoying block artefacts affecting picture quality.<br />
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Another challenge, as the silicon technology advanced for STi3240, STi3400, STi3500, STi3520, STi7000, STi5500 and successive derivative chips, was the memory bottleneck that became even more urgent to address due to the unified addressing space used by different accelerators. DRAM was costly and severely limited in space and bandwidth which in turn prevented the super integration since required to store I, P, B pictures and MPEG compressed bitstream. Decoding PAL and NTSC resolutions into only 16 Mbits of memory, to keep low the costs, implied several tricks to be implemented such as MPEG-2 B pictures decoding on the fly [4.4] and frame buffer compression [4.3] [4.5] [1.11] applied to both standard and high-definition decoders across the STi family. Novel memory reductions technique fixed the obstacle allowing MPEG SD decoding in only 8Mbits and HTDV in 32Mbits one of the most impressive achievement at that time.<br />
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The energy consumption obstacle needed to be addressed to avoid power hungry systems. SoC optimizations allowed to keep the power consumption challenge between 0.5 and 1 W because higher power consumption would have reduced dramatically the reliability of the chips which were not using any heat sink other than a plastic package. This allowed to increase speed and functionality up to full High-Definition pictures within a single chip, also addressing the engine orchestrating obstacle due the on-chip CPU, video, audio and graphics concurrent executions and later on, super integrating also the micro controller (8 to 32bits), which resulted into dramatically minimized costs and greatly improved performances, as compared with competition multi-chip implementations.<br />
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The STi family consisted of: STV3200 (DCT), STV3220 (Motion Estimator), STi3240, STi3400 (MPEG 1 video decoder), STi3500 (MPEG2 Video decoder), STi3520 (MPEG 2 audio and video decoder) and STi7000 (HD MPEG 2 video decoder and 3D graphics), STi5000 (integrating micro controllers) and many many others which we are not listing here for sake of brevity. <br />
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Using low pin count and plastic packages without heat sinks mitigated the manufacturing cost obstacle and increased reliability of those chips that also necessitated from a simple 8-bit micro controller to a more complex 32bits CPU as companion first and then integrated in the SoC. <br />
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In term of addressing the acceleration obstacle, by using such a deep hardware optimized design approach vs a full software one, the achieved performances were incomparable to state of art micro controllers such as 68020 which was unthinkable to be used due the excessive two digits number of them (to implement the decoding function) since 68020 was not optimized to process 60 or 120 million of pixels per second such the one required by high-definition MPEG 2 decoding. This need was further exacerbated later by the need to use on screen graphics to enhance used experience.<br />
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Another obstacle to address was user experience which required high quality images produced with real time graphics processing. This was addressed by super integrating incrementally powerful image blitters, on screen display processor, 3D and 2D vector graphics engines to support user interfaces, internet browsers, gaming and 3D TV. ST was the 1st in bringing 3D graphics to the digital consumer market by implementing OpenGL-ES and OpenVG standards from the Khronos group.<br />
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[[image:Figura9 graphics.png|thumb|Figure 9 graphic images rendered by STi family to enhance user experience]]<br />
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Organizational obstacles<br />
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At the beginning in 1986 the digital multimedia applications and services were not existing because of the analog TV transmissions were dominating in everyone entertainment life, while the PC one was marginal for that domain. By consequence, the SGS-THOMSON management was reluctant to invest initially in a full generation of STi chips with an unpredictable return on investment a-head. The internal investments were purely R&D without any revenues, just losses in term of money discouraging further investments. Moreover, the seed cooperation between Rennes Electronics Laboratory, ENST Paris and Thomson Semiconductor under DAII sponsorship since 1986 first, then with Apple computer and RCA removed those barriers and was instrumental for SGS-Thomson to create a roadmap of chips, manufacture them and to boost the chip production motivating subsequent investments and multimedia applications and service flourishment.<br />
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The architecture of the DCT chip was invented at ENST, [4.10] [4.11] [7.0], and the DCT industrial chip that was designed within the ENST laboratory (Alain Artieri spent a year in ENST team) using a specific CAD tool that was also developed within ENST, that made possible to generate this Hardware-Optimized solution. At that time, the head of the IC research group at ENST was Professor Francis Jutand, and Nicolas Demassieux was assistant professor. Nicolas Demassieux was personally participating to the MPEG1 (and later MPEG2) standardization efforts, and this work was fueled by EC-funded projects (such as the VADIS project). Both of Jutand and Demassieux came to SGS-Thomson, to convince the company managers to adopt DCT architecture and CAD tool. At that time, the internal ST design team was proposing 12 chips solutions, using gate-arrays. It took nearly a year to convince the manager of ST design team that Jutand and Demassieux had a credible solution, and a contract was signed between ENST and ST to a) licensing the intellectual property of two patents to ST, and 2) set-up a joint-design team that would design the DCT chip. Alain Artieri came for a year in the ENST team, and we designed together (with help of a couple of younger students) the layout of chip, while all the verifications (DRC, logical simulation....) were carried out in ST at Grenoble. Both Alain Artieri and Nicolas Demassieux designed the chip as equals in the collaboration.<br />
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The ST team in Grenoble should be hailed for this adventure, and for being open-minded to change their "usual way of working" and accept this innovative idea of a joint academic/industry design team, to deliver this world's first STV3200 chip. This was a unique case (to our best knowledge) of an industrial chip being designed by a joint academic/industry team, through the collaboration between ENST and ST. Initial research work at ENST in 1986, described in [1.24]. [4.10] [4.11] patents granted to ENST in 1986 resulting from this research. Licensing and contractual agreement between ST and ENST during 1986 with final meeting to close the deal on Nov 12, 1986.<br />
<br />
A key management directive was to seek the market interest on those chips and an initial customer which was Apple Computer with whom SGS-Thomson specified the first MPEG1 ST3240 chip using available STV3200 implementing DCT. Secondly RCA, acquired by Thomson Consumer Electronics, was massively investing on Digital Satellite broadcast but its end-to-end system was lacking affordable decoding technologies. SGS-Thomson management decision was to take the risk on the decoder development without any commitment from RCA, with potential loss of development costs. Thanks to the deep hard work of SGS-Thomson a key engineer like Alain Artieri, it was released to RCA, one and half year ahead of C-Cube therefore being the first decoder being adopted into DirectTV digital multimedia broadcast.<br />
|a5=As reported into [1.9] many solutions for image and compression ICs were existing in 1992 however SGS-Thomson started since 1986. The ST innovations, which have been outlined in this IEEE Milestone proposal and which have created and provided significantly advancements in the field of digital multimedia, can be concisely summarized as follows:<br />
<br />
1) The silicon development started on 1986 between Rennes Electronics Laboratory, ENST Paris and Thomson Semiconductor under DAII sponsorship a-head of anybody else<br />
<br />
3) The 1st chip for mass production for forward and inverse DCT was STV3200 in 1988.<br />
<br />
4) The 1st chip for mass production for motion estimator was STV3220 in 1989.<br />
<br />
5) Their hardwired implementations replaced software solutions which needed hundreds of Motorola 68020 which were unable to achieve production and deployment into end user Set top boxes and digital TV.<br />
<br />
6) They incrementally implemented innovative techniques to reduce memory bandwidth such as block based efficient burst memory read and write, picture decoding on the fly, frame buffer compression to minimize external RAM needs and enable super integration of 1 bit transistor memory RAM cells in an on per requirement fashion.<br />
<br />
7) Gave the designer the freedom to use more advanced CMOS silicon lithography such as 0.5, 0.35um and successive in order to achieve super integration of more and more functionalities, to meet affordable mass production.<br />
<br />
8) Integrate more heterogeneous functions such as micro controller (8 bits, 32bits), audio decoding and 3D OpenGL-ES graphics<br />
<br />
9) System on Chip integration including faster processor cores (high instruction per cycles and frequency), caches (to handle code density and latency), memory controllers (for minimal latency communication with DDR), assisted by tool chains (with compilers adopted by a wide developer community) <br />
<br />
10) Addressing HDTV decoding, Video encoding and content Transcoding in real time<br />
<br />
11) Super integrating MPEG2 transport processing capabilities using STM32 bit microprocessor.<br />
<br />
12) Low dissipation <1W (figure 10) and high throughput efficiency<br />
<br />
[[image:Figure10 power consumption.png|thumb|Figure 10 Power dissipation minimized by STi family under 1W ]]<br />
<br />
13) A continued investment on R&D and production started on 1986 till 2016 for 30 years of break-through products that shaped the digital multimedia domain (figure 11). <br />
<br />
[[image:Figure11 mpeg.png|thumb|Figure 11]]<br />
|references=1. TECHNICAL ARTICLES, CONFERENCE PAPERS & BOOKS<br />
<br />
[1.1] A. Artieri, S. Kritter, F. Jutand and N. Demassieux, "A one chip VLSI for real time two-dimensional discrete cosine transform," 1988., IEEE International Symposium on Circuits and Systems, 1988, pp. 701-704 vol.1, doi: 10.1109/ISCAS.1988.15022.<br />
<br />
[1.2] STV3200 DISCRETE COSINE TRANSFORM (DCT) Datasheet<br />
<br />
[1.3] A. Artieri and F. Jutand, "A versatile and powerful chip for real-time motion estimation," International Conference on Acoustics, Speech, and Signal Processing, 1989, pp. 2453-2456 vol.4, doi: 10.1109/ICASSP.1989.266964.<br />
<br />
[1.4] STi3220 MOTION ESTIMATOR PROCESSOR Datasheet<br />
<br />
[1.5] APPLICATION NOTE STi3220 MOTION ESTIMATION PROCESSOR CODEC<br />
<br />
[1.6] STi3400 MPEG/H.261 VIDEO DECODER DATASHEET<br />
<br />
[1.7] STi3500 MPEG2 CCIR 601H.261 VIDEO DECODER DATASHEET<br />
<br />
[1.8] Image and Video Compression standards: algorithm and architectures, Bhaskaran, Vasudev, Konstantinides, Konstantinos, ISBN 978-1-4615-6199-6, 1995<br />
<br />
[1.9] K. Konstantinides and V. Bhaskaran, "Monolithic architectures for image processing and compression," in IEEE Computer Graphics and Applications, vol. 12, no. 6, pp. 75-86, Nov. 1992, doi: 10.1109/38.163627.<br />
<br />
[1.10] A. Artieri and O. Colavin, "A chip set core for image compression," in IEEE Transactions on Consumer Electronics, vol. 36, no. 3, pp. 395-402, Aug. 1990, doi: 10.1109/30.103150.<br />
<br />
[1.11] A. Chimienti, M. Lucenteforte, D. Pau and R. Sannino, "A novel co-decoding scheme to reduce memory in MPEG-2 MP@ML decoder," 1998 URSI International Symposium on Signals, Systems, and Electronics. Conference Proceedings (Cat. No.98EX167), 1998, pp. 272-277, doi: 10.1109/ISSSE.1998.738080.<br />
<br />
[1.12] STi70000 press release<br />
<br />
[1.13] STi71000 datasheet<br />
<br />
[1.14] STi7200 datasheet<br />
<br />
[1.15] STi7108 datasheet<br />
<br />
[1.16] STi7108 processor with 3D graphics made public.<br />
<br />
[1.17] A chip set for MPEG-2 video encoding; Proceedings of the IEEE 1995 Custom Integrated Circuits Conference, 1995 <br />
<br />
[1.18] STi3240 MPEG1/H261 datasheet<br />
<br />
[1.19] STi3208 DCT chip datasheet<br />
<br />
[1.20] STi3520A MPEG2 chip datasheet<br />
<br />
[1.21] STi5600 MPEG2 chip datasheet<br />
<br />
[1.22] STi5610 MPEG2 chip datasheet<br />
<br />
[1.23] R. Bruni, A. Chimienti, M. Lucenteforte, D. Pau and R. Sannino, "A novel adaptive vector quantization method for memory reduction in MPEG-2 HDTV decoders," in IEEE Transactions on Consumer Electronics, vol. 44, no. 3, pp. 537-544, Aug. 1998, doi: 10.1109/30.713161.<br />
<br />
[1.24] F. Jutand, N. Demassieux, G. Concordel, J. Guichard and E. Cassimatis, "A single chip video rate 16×16 discrete cosine transform," ICASSP '86. IEEE International Conference on Acoustics, Speech, and Signal Processing, 1986, pp. 805-808, doi: 10.1109/ICASSP.1986.1169147.<br />
<br />
[1.25] N. Demassieux, G. Concordel, J. Durandeau and F. Jutand, "An optimized VLSI architecture for a multiformat discrete cosine transform," ICASSP '87. IEEE International Conference on Acoustics, Speech, and Signal Processing, 1987, pp. 547-550, doi: 10.1109/ICASSP.1987.1169851.<br />
<br />
[1.26] Tomasko, M., Buchhauser, D., Bushroe, M. et al. The Descent Imager/Spectral Radiometer (DISR) Experiment on the Huygens Entry Probe of Titan. Space Science Reviews 104, 469–551 (2002). https://doi.org/10.1023/A:1023632422098<br />
<br />
2. ONLINE INFORMATION AND CITATIONS<br />
<br />
[2.1] https://en.wikipedia.org/wiki/Motorola_68020 <br />
<br />
[2.2] https://techmonitor.ai/technology/sgs_thomson_debuts_one_chip_hdtv_system <br />
<br />
[2.3] Leonardo Chiariglione awards https://leonardo.chiariglione.org/public-life/awards/ <br />
<br />
[2.4] see pdf and https://www.eetimes.com/apis-help-stmicroelectronics-grow-set-top-box-business/# <br />
<br />
[2.5] see pdf and https://www.edn.com/sgs-thomson-microelectronics-named-number-one-mpeg-decoder-supplier-by-dataquest/ <br />
<br />
[2.6] see pdf and http://www.fundinguniverse.com/company-histories/stmicroelectronics-nv-history/ <br />
<br />
[2.7] https://books.google.it/books?id=C-bgBwAAQBAJ&pg=PA234&lpg=PA234&dq=stv3200+sgs-thomson&source=bl&ots=HrOQA0LEvS&sig=ACfU3U0vpZ7K5HJzJ1qJWjjlk4yfzPW82w&hl=it&sa=X&ved=2ahUKEwj2lZ2p35HwAhWBzKQKHVrmBBMQ6AEwEnoECBUQAw#v=onepage&q=stv3200%20sgs-thomson&f=false <br />
<br />
[2.8] http://www.quretec.com/u/vilo/edu/2002-03/Tekstialgoritmid_I/Loengud/Loeng7_Compression/www.faqs.org/faqs/compression-faq/part1/preamble.html<br />
<br />
[2.9] https://books.google.fr/books?id=UsH8CAAAQBAJ&lpg=PA501&ots=OJr_PN0LKo&dq=stv3200%20DCT&hl=fr&pg=PA501#v=onepage&q=stv3200%20DCT&f=false <br />
<br />
[2.10] http://ciclops.org/ir_index/208/In-Orbit?js=1 <br />
<br />
<br />
3. STMicroelectronics documents<br />
<br />
[3.1] De la Transformée en Cosinus Discrète aux Processeurs Applicatifs Multimédia, Alain Artiéri, Septembre 2007, STMicroelectronics presentation<br />
<br />
4. PATENTS<br />
<br />
[4.1] Integrated signal processing circuit for online and column summation of digital value matrices https://patents.google.com/patent/FR2608802B1/en?inventor=alain+artieri&oq=alain+artieri&sort=old <br />
<br />
[4.2] Transposition memory for data processing circuit https://patents.google.com/patent/FR2617621B1/en?inventor=alain+artieri&oq=alain+artieri&sort=old <br />
<br />
[4.3] Method and apparatus for addressing a memory area of an MPEG decoder4.6<br />
<br />
[4.4] publication number US6081298A MPEG decoder with reduced memory capacity<br />
<br />
[4.5] ITVA960016D0 Metodo di ricompressione e decompressione adpcm di un flusso di dati digitali costituente un segnale video digitale e stimatore https://patents.google.com/patent/ITVA960016D0/it?inventor=danilo+pau&oq=danilo+pau&sort=old<br />
<br />
[4.6] publication number 0 298 002 of 29.06.1988 Memoire de transposition pour circuit de traitement de donnes<br />
<br />
[4.7] publication number FR2649226A1 BREWING CIRCUIT OF DATA<br />
<br />
[4.8] publication number FR2650462B1 Device for converting a line scanning into a scanning in vertical saw teeth by bands; https://patents.google.com/patent/FR2650462B1/en?q=H04N3%2f30&inventor=alain+artieri&sort=old <br />
<br />
[4.9] publication number EP0368731B1 Process and circuit for image representation signal filtration<br />
<br />
[4.10] Circuit pour effectuer une transformation linéaire sur un signal numérique Patent issuer and number eu EP 0241352 A1 https://patents.google.com/patent/EP0241352A1<br />
<br />
[4.11] Additionneur binaire comportant un opérande fixé, et multiplieur binaire parallèle-série comprenant un tel additionneur Patent issuer and number eu EP 0262032 B1 https://patents.google.com/patent/EP0262032B1 <br />
<br />
5. Honors<br />
<br />
[5.1] Two European IT Prizes Awarded to STMicroelectronics<br />
<br />
6. MPEG mentions<br />
<br />
[6.1] Chiariglione and the birth of MPEG https://www.chiariglione.org/public-life/media/leonardo_ieee/prof.htm <br />
<br />
7. Letters of support<br />
<br />
[7.0] Endorsement by Leonardo Chiariglione, Nicolas Demassieux, Senior Vice President of<br />
Research, Orange, assistant professor at ENST (now Telecom ParisTech) mid 80s.<br />
<br />
[7.1] Endorsement by Leonardo Chiariglione, the father of MPEG<br />
<br />
[7.2] Endorsement by Prof Rocca, pioneer of motion estimation in 1969<br />
<br />
[7.3] Endorsement by Hisafumi Yamada, former Sony US TV CTO<br />
|submitted=Yes<br />
}}</div>Administrator1http://ieeemilestones.ethw.org/index.php?title=File:Figure11_mpeg.png&diff=11025File:Figure11 mpeg.png2021-05-12T15:30:52Z<p>Administrator1: </p>
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<hr />
<div>{{Proposal<br />
|litigation=No<br />
|more than 25 years=Yes<br />
|within fields of interest=Yes<br />
|benefit to humanity=Yes<br />
|regional importance=Yes<br />
|ou is paying=Yes<br />
|ou is arranging dedication=Yes<br />
|section is taking responsibility for plaque=Yes<br />
|a11=Yes<br />
|a3=1986<br />
|a1=Multimedia Integrated Circuits for MPEG, 1986<br />
|plaque citation=SGS-THOMSON (now STMicroelectronics) pioneered the family of multimedia integrated circuits, accelerating Moving Picture Experts Group (MPEG) standards. Discrete Cosine Transform designed with ENST (now Telecom ParisTech) was the first. Innovative memory reduction techniques, highly optimized dedicated hardware accelerators, super-integration of heterogeneous processor units achieved significant performances and cost reduction with minimized energy consumption. These integrated circuits were the key enabler of digital multimedia services to entertain end-users in everyday life.<br />
|a2b=France Section<br />
|IEEE units paying={{IEEE Organizational Unit Paying<br />
|Unit=France<br />
|Senior officer name=Claire LAJOIE-MAZENC<br />
|Senior officer email=claire.lajoie-mazenc@rte-france.com<br />
}}<br />
|IEEE units arranging={{IEEE Organizational Unit Arranging<br />
|Unit=France with STMicroelectronics<br />
|Senior officer name=Claire LAJOIE-MAZENC<br />
|Senior officer email=claire.lajoie-mazenc@rte-france.com<br />
}}<br />
|IEEE sections monitoring={{IEEE Section Monitoring<br />
|Section=France<br />
|Section chair name=Claire LAJOIE-MAZENC<br />
|Section chair email=claire.lajoie-mazenc@rte-france.com<br />
}}<br />
|Milestone proposers={{Milestone proposer<br />
|Proposer name=Danilo Pau<br />
|Proposer email=danilo.pau@st.com<br />
}}{{Milestone proposer<br />
|Proposer name=Jean-Michel Moutin<br />
|Proposer email=jean-michel.moutin@st.com<br />
}}<br />
|a2a=(45.203333, 5.695833)<br />
|a7=The Grenoble site is of premier importance for STMicroelectronics since was owned by THOMSON SEMICONDUCTEURS and then merged with SGS in 1987 to form SGS-Thomson (now STMicroelectronics). Nowadays is the biggest R&D site of STMicroelectronics, hosting many product divisions from the three Product Groups of the company, including silicon and software design, test, and advanced packaging developments. The site were MPEG chips were conceived and designed<br />
|a8=Yes, even if part of them were restructured they still exists @ STMicroelectronics, 12, rue Jules Horowitz F-38000 Grenoble, France<br />
|mounting details=Plaques will be installed in a public place at the main entrance as shown below. It will be close to ST security personnel who are is monitoring entrance 24 hours in a day, every day in a year. Very close as indicated there are other public roads. Plaque will be placed at 12, rue Jules Horowitz F-38000 Grenoble, France. GPS coordinates are: 45°12’12” N ; 05°41’45” E (45.203333, 5.695833). Therefore, visitors will not need to be escorted by ST guards to look the plaque or to take a snapshot of it. The milestone plaque will be installed right in front of STMicroelectronics, main entrance access. It is where employees, visitors and customers must pass to get into the ST Grenoble offices on daily basis. It is monitored continuously 24h/7d by ST security human resources and surveillance camera. It is a public place, right outside ST site restricted perimeter.<br />
|a9=It is protected by ST security human resources and with surveillance camera, 24h/7d. It is publicly and easily accessible from 12, rue Jules Horowitz F-38000 Grenoble, France. The site can be reached also from Lion Airport, close to Grenoble as shown in figure 2.<br />
|a10=STMicroelectronics (Grenoble 2) SAS<br />
|a4=The technology objective of STMicroelectronics was to conceive, ahead of MPEG standard, and introduce innovative hardware solutions able to achieve several order of magnitude speed acceleration, compared to unfeasible full software implementation of MPEG decoding and encoding functionalities, by introducing for the first time memory compressions and reductions, dedicated hardware implementation in order to save silicon area per technology node, super integrate new functionalities in a less than a watt power envelope. <br />
The DCT circuit, the first in the family, was so reliably designed and produced that was subsequently used in the Cassini-Huygens probe for transmitting compressed images of Saturn during 20 years.<br />
Specific objectives, that motivated STMicroelectronics (short name ST) to pioneer Mpeg family of System on a Chips and associated CMOS silicon technology development to implement it and starting since 1987 and onward, were:<br />
<br />
1) To create reliable and low complex CMOS building (integrated circuits) blocks at production maturity to dramatically accelerate real time MPEG video decoding and encoding functionalities at increasing image resolutions and frame rates.<br />
<br />
2) To super-integrate such building blocks in more complex integrated circuits and SoCs to accelerate MPEG 1, 2, 4, H264, HEVC and subsequent standardized specifications, at the same time they were under development. In other words before the standards were officially frozen and went public.<br />
<br />
3) To achieve lowest on chip memory footprint and bit-depth of computing data paths to dramatically save silicon area given the existing (µm) CMOS technology constraints for mass production and reliable manufacturability with marginal chip defectivity.<br />
<br />
4) To achieve minimal power consumption, to and below 1W across different silicon technologies generations and starting from 1.2um silicon gate manufacturing processes. Successive lower dimension lithography, were needed considering an increasing need to super integrate functionalities, heterogeneous hardware accelerators, microprocessors, graphic engines, crypto engines, a rich set of peripherals and interfaces etc.<br />
<br />
5) To remove any need of costly and bulky heat-sinks as well as complex cooling mechanisms to offer an easier viable integration into thinner video equipment manufactured systems.<br />
<br />
6) To dramatically reduce as low as possible video communication bandwidth between the chip and the external DRAM memories to minimize memory requirements of those chips and associated costly power consumption.<br />
<br />
7) To control those chips with very simple and low computing power 8bits micro controllers and incrementally as requirements will grew with 32 bits: this to support flexibility that requires further software computing needs to offer un precedented user experience. Including the use of advanced graphics to ease content accessibility and fruition.<br />
<br />
8) To enable viable, widely adopted, broad range of diversified digital multimedia applications and services, implying affordable software development and deployment to a vast range of end users at worldwide level with different needs.<br />
<br />
In the following there is the summary of achievements by STi family in the present milestone proposal. To meet the above-mentioned challenging objectives and long-term technology vision, ST, since 1986, has developed following key technologies and chips. A few but very relevant technologies and chips will be described, because the family is too huge to report completely in this document.<br />
<br />
1) Seminal work on ST CMOS technologies, started at ENST [1.24] [1.25] [7.0] with Thomson Semiconductors (now STMicroelectronics), produced the architecture of an economically reasonable chip implementing various sizes DCT 16x16, 16x8, 8x8, 8x4, 4x4. The main features of the chip under development with THOMSON SEMICONDUCTEURS in 2 µm first and then 1.25 µm CMOS technology were 70,400 Transistors, 25 mm2, Internal clock 13.5 MHz, Direct/Reverse DCT, 8 bits pixels, 16 bits internal accuracy. The chip was sampled by THOMSON SEMICONDUCTEUR in October 1987.<br />
<br />
2) STV3200 [1.1] [1.2] was a dedicated integrated circuit to accelerate the discrete cosine transform (DCT). The two-dimensional forward DCT (FDCT) and inverse DCT (IDCT) was implemented for various image block sizes and the pixel rate was up to 15.0 MHz The circuit architecture was fully bidirectional with a 9-bit magnitude pixel data bus and a 12-bit magnitude coefficient data bus programmed as input or output depending on the selection of Forward DCT or Inverse DCT function. DCT was so complex that to be implemented on a CPU required about 1 billion additions per second (1 giga Hertz operations per second) to process the moving pictures in real time. CPUs and CMOS silicon process were unable to achieve such a very high frequency, therefore implying the computing power of fifty Motorola 68020 [2.1], one of the faster micro-processors in the 1980s. The integrated circuit went officially in production at the end of 1987 and was a world premiere product. Since 1988, this component was successfully sold by SGS-Thomson. It implemented key patents [4.1][4.2] for rearranging, permuting or selecting data according to predetermined rules, for changing the order of data flow, e.g. matrix transposition, LIFO buffers; Overflow or underflow handling that were key for DCT and IDCT implementations.<br />
<br />
Innovative memory footprint reduction and distribution techniques were used since the hardware design did not use the traditional architecture (such as a unique multiplier that would read/write in a large memory), but a bit-serial pipelined architecture, where memory was distributed across the chip, to feed the 16 bit/serial dedicated multipliers that the chip had.<br />
<br />
The STV3200 chip was used in the DISR (descent imager) [1.26] [2.9] [7.0] of Cassini-Huygens probe that was launched in 1997 and has transmitted magnificent images of Saturn until 2017. All the wonderful images that are available in this site [2.10] have been processed through the chip!<br />
<br />
Design of the STV3200 happened during the December 1986 to August 1987 period (product sampling around October 1987) as mentioned at the end of [1.25]. As said commercialization of the STV3200 started in 1988 while on November 1988 there was the publication of the H261 standard (1st standard using DCT for real time video coding) and on May 1988 there was the 1st meeting of the MPEG standard (that was published in 1993).<br />
<br />
Figure 3 DCT chip<br />
<br />
3) STi3220 [1.3] [1.4] [1.5] was the second member of the family, a real time motion estimation integrated chip dedicated to motion estimation at video rates. The chip was optimized to compute the displacement vector of 8x4n or 16x4n pixel blocks in a search window, between temporally distant pictures, defined by a maximum horizontal and vertical displacement of +7/-8 pixels corresponding to 256 different vectors. The chip computed 256 distortion for each block according to the MAE (mean absolute error) criteria. The motion estimation required about 4 billion of additions per second (4 giga Hertz operations per second). If it would be implemented on CPU it would require the equivalent computing power of several hundred of Motorola 68020. Therefore, it was unfeasible in software. Its development started in 1988, went in production and be sold by SGS-Thomson since 1989. This component was another world premiere product in conjunction with STV3200. Furthermore, the Motion estimation processor was a key building block to accelerate more complex MPEG-2 Video Encoders [1.17]<br />
<br />
4) Super integration of those fundamental functions with others fundamental building blocks (e.g. scalar quantization and de-quantization, entropy coding and decoding, motion compensation, unified memory management), was the next vital step required to manufacture reliable system solution for mass production while before they were consisting of few chips. In this respect [1.20] presents the deployment of STV3200 and STi3220 in a complete video codec hardware architecture for high pixel rates addressing standard (SD) and high definition (HD) picture formats.<br />
<br />
5) STi3240 [1.18] was the 1st MPEG1/H261 chip with STV3208 (DCT processor) [1.19] supporting video decoding schemes up to 10 Mbit/s of the ISO/MPEG future (at that time under active definition) video standard and CCITT/H261 recommendation at video rate (352x288 pixels at 30fps). It required between 512 KBytes up to 4Mbytes of external DRAM with a 8/16 bits microprocessor interface. External DRAM was a scarce and costly resource, dramatically impacting the overall power consumption and bill of material. Therefore, the use of memory reduction techniques to support high chip calculations throughput and minimized data bandwidth between the chip and the memory were conceived for the first time and implemented.<br />
<br />
Figure 4 decoder system, STV3208 was DCT co processor<br />
<br />
6) Then the super integration of way started with active development of System of Chip. Earliest members of the STi digital multimedia chip family for mpeg moving picture processing were: STi3400, STi3500, STi3520A. Other early examples were STi7000, STi5000 (and the very many others that followed). They were the first able to offer a dramatic reduction in silicon and package size, power consumption, with higher level of transistors integration, functionalities, and lowest cost of equipment’s. Such equipment’s were made previously by many un-optimized discrete signal processors (DSP) and which were placed into many more boards. They far from being manufacturable viably and affordably for MPEG-1 and MPEG-2 standards deployment at end user side. STi chips were very instrumental to accelerate the introduction to the end users of CD-ROM, DVDs, Set Top Box and digital TVs that became ubiquitously adopted throughout the entertainment world and in everyone home (and mobile phones) across 3 decades.<br />
<br />
7) Inside those chips’, innovative and advanced reduction techniques of external memory bandwidth were conceived and implemented first. They were key to lower power consumption to and under 1W. In that respect several key methods are described in the following subsections:<br />
<br />
a) block based pixel memory addressing and communication [4.3] allowed to minimize the cost of external memory page openings and closures, distributing the costly overhead per block size (composed by several pixels) instead of per single or per few pixels. In turn this allowed to avoid hardware pipeline stalls resulting in using peak performances and resulting in a full motion interactive frame rates, clear picture decoding, free from block artefacts<br />
<br />
b) picture decoding on the fly [4.4] was a break-through technology to decompress and motion compensate at the same time while displaying MPEG B-pictures. This to avoid inefficient and further storage of them in the external frame buffer, thus resulting in a dramatic reduction of the external memory to only 16 Mbits for SD definition [1.20]<br />
<br />
c) frame buffer compression [1.11] [4.5] was another key technology used to co-decompress on the fly I , P and B MPEG pictures by halving the associated external DRAM memory and the memory bandwidth without annoying picture artefacts. Indeed, in STi solution the quantization noise was cleverly masked by MPEG coding noise, resulting in not human perceivable loss of quality. This allowed to reach 8 Mbits DRAM footprint in SD enabling super integration of 1 bit transistor per cell DRAM on the same chip, in a more competitive way than integrating 6 transistor per cell SRAM. Since then STi did not require any additional external memory for the MPEG SD video decompression task. Another kind of memory reduction was applied to HDTV decoders with even further benefits. [1.23] was novel method to reduce the external memory needed by STi MPEG-2 HDTV decoder architecture. The total amount of memory was reduced from 96 to 32 Mbits preserving a good picture quality. Furthermore, it required low hardware complexity increases of less than 5%, in 0.35 pm technology, the total decoder silicon area with respect to the standard decoder.<br />
<br />
8) The STi implementation of the ST comprehensive vision to create the digital Multimedia domain was made possible with those and many other chips. <br />
<br />
However, the pioneering development work began since 1986 [1.24] [1.26] among different and key French partners:<br />
<br />
1) Thomson Semiconductor (merged later into SGS-THOMSON, now STMicroelectronics) launched innovative circuit architecture studies for integrated for the Discrete Cosine Transform since 1986<br />
<br />
2) ENST Paris (now Telecon ParisTech) was very active and interested since 1986 in integrated circuit architectures for DCT [1.24] [1.25] single chip for video rates.<br />
<br />
3) Rennes Electronics Laboratory, expert in the field of image compression, built image transmission equipment between studios and digital recording.<br />
<br />
Under the finance support of the DAII (French State Agency) these three laboratories collaborated to form a team responsible for realizing the first DCT component (STV3200) and the Motion Estimation chip (STi3220). The DCT and Motion estimation chips existed thanks to the strong collaboration between SGS-Thomson and the public research lab of ENST.<br />
<br />
Thus, on 1988, SGS-THOMSON finalized these seminal developments in production (but with background developments since 1986 [1.24] [1.26] in Thomson Semiconductor) therefore creating the wave of key circuits and SoC for MPEG. By consequence it mastered at industrial level initially the 2 key components which made possible and economically viable the realization of more complex, reliable, ready for mass production, yet low cost and low power MPEG-1 and MPEG-2 encoders and decoder systems for the (mid 80s) for the not existing digital multimedia television markets. <br />
<br />
9) Apple Computer was looking for a technology partner in the field of image compression. Since aware of above-mentioned developments, contacted SGS-THOMSON in 1988. The 68020 microprocessors was used from March 1987 to March 1992 and only used twice, once in the Macintosh II as a high-end processor, and then again with the Macintosh LC, as a low-end processor. However, it was too slow and inadequate to support video decoding functions as for MPEG decoding. From this key technical limit, a collaboration with SGS-Thomson was started, the first in its kind, to study and develop highly integrated set of components to provide video functions for Apple's microcomputers. That was a very advanced concept for that time. <br />
Therefore SGS-THOMSON entered a partnership with Apple. Thus, based on SGS-THOMSON understanding of 68020 limits and the contribution of innovative chip solutions from SGS-THOMSON, the first architecture of an integrated system for image compression was defined to support the MPEG1 standard: the STi3240 [1.18], STi3400 [1.6]. STi3400 was a real time video, super integrated with DCT, decompression integrated processor supporting MPEG-1 and H.261 standards. The digital output was for PAL 50Hz and NTSC 60 Hz interlaced displays.<br />
<br />
10) Next leveraging his expertise, SGS-THOMSON started a background work with RCA, which ended in 1992 with the development of an MPEG2 video decoder, STi3500 [1.7] and subsequent STi3520 [1.8]. Those were other essential components at the heart of the revolutionary multimedia digital television services introduced firstly from the USA Digital Satellite DirectTV firm. SGS-THOMSON succeeded in delivering the first MPEG2 decoder in the world, much ahead of the Californian start-up C-CUBE. It must be noticed that C-Cube was funded on 1988 when SGS-THOMSON had already above-mentioned chips in production and when Thomson semiconductor started on 1986. <br />
<br />
11) STi3500 was a real time video decompression integrated circuit supporting MPEG-1 and MPEG-2 standards at video rates up to 720x480x60Hz or 720x576x50Hz requiring minimal support from an external 8bit microcontroller (ST8) used only to initialize the chip, reducing the complexity of software and associated code footprint. It required only 1W of power consumption. The STi3500 was a success since achieved a turnover greater than $ 100M in less than 3 years as a sign of market adoption. In that chip STV3200 (which was super integrated) represented only 10% of the total silicon area. STi3520 on top of STi3500, used only 16Mbits memory and integrated audio decoder compliant with MPEG layers I and II supporting sampling rates of 32, 44.1 and 48 KHz. STI3520A [1.20] was a single chip for MPEG MP@ML video decoding in only 16 Mbit RAM integrated with STi4500 MPEG L1 and L2 Audio decoder and integrating on screen display generator. The chip was using 0.5µm CMOS SGS-THOMSON technology<br />
<br />
12) STi7000 [1.12] [2.2] was an integrated system for High-Definition Television (HDTV), which combined an MPEG-2 decoder with a display and format converter onto one chip in 1998. As already introduced in point 5) the most advanced trick was the frame buffer memory reduction through tiny on chip compression engine based on scalar adaptive quantization allowing full HDTV pictures to be decoded and displayed with only 64 Mbits of external memory instead of 128 Mbits. Designed for use in HDTV and other digital TV receivers, set top boxes and PCs, the STi7000 was developed in collaboration with Thomson Multimedia, a strategic partner with whom SGS-THOMSON shared a joint design center in Grenoble, France. The chip incorporated all the 18 video formats defined by the ATSC (Advanced Television Systems Committee) and Grand Alliance specifications. STi7000 supported video rates of up to 1920 x 1088 x 30Hz interlaced or 1280 x 720 x 60Hz progressive. Built in 0.35-micron SGS-Thomson HCMOS6 silicon technology, the STi7000 also included interfaces for a host microcontroller, local SDRAM, standard or high-definition video output and D1 digitized video input. Next versions STi7100 [1.13] STi7200 [1.14] also integrated graphics engine and power powerful micro controllers. STi7108 had dual ST40-300 CPU host processors linked to a 256K L2 cache giving up to 2000 DMIPS performance and a total of 4000 DMIPS. A 3D graphics engine [1.15] enabled advanced Internet content and high-performance gaming. It was the first set-top box IC [1.16] in the market to combine 3D OpenGL-ES 2.0 graphics, Ethernet, USB and e-SATA interfaces to connect Internet devices, DVR storage or external Flash or hard-disk (HDD) drives. <br />
<br />
13) The STi5500 was the first member of back-end decoders for set-top boxes and DVD players. Compliant with MPEG-2 to decode its transport stream and convert it into sounds and images that sent to loudspeakers, monitors, TV screens and similar human interfaces. The STi5500 was the first integrated circuit in the world to incorporate not only all the circuitry required to handle all the back-end functions but also a 32-bit microprocessor. The built-in microprocessor had sufficient processing power to handle system-level functions as well as the managing the MPEG decoding function, so it eliminated the need for a separate system controller in most applications. Its super integration was the crucial factor and achieved immediate customers adoption. Since then, ST has developed even more powerful members including the STi5505, which is the first silicon chip in the world to integrate all the back-end functions of a DVD player. <br />
As demonstration of the innovation it brought in the field of digital multimedia, STi5500 won [5.1] from a field of nearly 300 nominations, the prestigious European IT PrizesPrize awarded by the European Commission in conjunction with Euro-CASE, the European Council of Applied Science and Engineering, for the development of products that are expected to play fundamental roles in helping European industry to increase its share of world markets.<br />
<br />
Summarizing SGS-THOMSON STi gained its leadership position in the field of digital consumer multimedia decoder-type products for digital satellite TV and DVD players. Early members such as STV3200, STi3220, STi3240, STi3400, STi3500, STi3520A, STi7000, STi7100, STi7108, STi5500 SoC through the 80s, 90s and 2000 years continued for the development of digital multimedia applications at heart of the worldwide digital multimedia convergence of the TV services for everyday users, the world of telecommunications and the world of the PC. <br />
<br />
Many other generations were manufactured across the years as shown in the next figure 5 even supporting complex operative systems such as Linux.<br />
<br />
Figure 5<br />
<br />
Interestingly many decades later, the pioneering work that conducted to STV3200 represented less than 0.1% of the surface of the SoC (figure 6). <br />
<br />
Figure 6 Super integration of DCT with other multimedia functions<br />
<br />
Until STMicroelectronics has sold over 500,000,000 (cumulated) of those integrated systems worldwide. This figure undoubtedly demonstrates the pervasive of STi family through the world. Figure 7 shows cumulative shipments of ST products per year basis.<br />
<br />
Figure 7<br />
<br />
14) As proof of the high relevance of the proposed milestone a number of letter of supports were provided by key and well know experts in the field<br />
<br />
a) A letter of endorsement [7.0] to ST milestone is provided by Nicolas Demassieux, Senior Vice President of Research, Orange [2.3], and assistant professor at ENST (now Telecom ParisTech) working on very optimized VLSI implementations for signal processing, included the DCT processor.<br />
<br />
b) A letter of endorsement [7.1] to ST milestone is provided by Leonardo Chiariglione [2.3], the father of MPEG and the driving force behind MPEG standards for digitized video. Leonardo is unanimously considered a genius since created a new way of enjoying music, with Leonardo Chiariglione’ s MP3 standard.<br />
<br />
As mentioned in the public article [6.1] with Leonardo Chiariglione, SGSThomson has been a big MPEG driver since it was the world's leading producer of MPEG-related ICs and supplied close to 70 percent of the world's MPEG-2 decoder chips. That was the result of the audiovisual vision that was shared by the leaders of SGS-Thomson, Thomson Multimedia SA, Paris, and France's government. Also, Chiariglione noted, Thomson's U.S. subsidiary RCA was in the need of MPEG chips for a huge order of 1st generation satellite TV decoders--a million set-top boxes for the Hughes-RCA DirecTV newborn system--and SGS-Thomson Microelectronics got the contract, as proof of its leading integrated circuits technology started since 1986.<br />
<br />
c) A letter of endorsement [7.2] to ST milestone is provided by prof Fabio Rocca. Prof Rocca on 1969 was the pioneer on motion estimation and compensation technologies.<br />
<br />
d) A letter of endorsement [7.3] to ST milestone is provided by Hisafumi Yamada, past Sony USA TV CTO that prove the high innovation STi HDTV chips provided to ATV USA television.<br />
<br />
15) In the following years STi products on MPEG where the key enabling factor of a huge digital consumer ecosystem composed by many operators, equipment manufacturers, software developers and conditional access companies as shown in the next figure 6<br />
<br />
Figure 8 Worlds wide level ecosystem for digital multimedia services created thanks to STi family<br />
<br />
16) As written in the EETimes article [2.4] “In the first shift or wave (referred to in the set-top box market) , which began about 1994, the boxes were simple channel-hopping devices for satellite and cable TV providers, Hatch explained. (ST's MPEG-2 video decoders were used then in the boxes manufactured by Thomson's RCA subsidiary.)” which clearly witness how ST was ahead.<br />
<br />
17) As written in the EDN article [2.5] on 1996 “Dataquest has confirmed SGS-THOMSON Microelectronics (Lincoln, MA) as the world's leading supplier of MPEG decoder ICs in 1995.” which witnessed ST leadership on MPEG decoders.<br />
<br />
18) as written into a public article STMicroelectronics NV History [2.6] quoting “ ST is the world's leading manufacturer of analog ICs (integrated circuits) and MPEG-2 decoder chips, used to provide video decompression for DVD players and digital television set-top boxes.” and “Another area in which SGS Thomson became an early player was its development of MPEG decompression chips. The company's dedication to MPEG technology was risky, as a number of other digital video decompression schemes were competing for what promised to be a huge market in the future. SGS Thomson gained an early lead in the MPEG market, however, releasing its first Motion Estimation Processor in 1990. By 1993, the company had debuted its "multimedia" chip, capable of decompressing digital video files for display on a television set. This chip helped the company take a major position in the new set-top box market, starting with supplying the chip for the Hughes digital satellite television set-top box.” It helps to also state that ST was dominating the MPEG domain winning over the risks due to its early investments.<br />
<br />
19) SGS-THOMSON was also not only pioneer of MPEG2 in satellite digital multimedia business with DirecTV but also in Cable business with Scientific Atlanta (which was acquired by Cisco later). Thanks to the collaboration the STi chips named 5600 and 5610 were the first chips to integrate graphics engine with multimedia processors [1.21], [1.22].<br />
|a6=One key initial obstacle was represented by the initially used 1.2 um silicon technology that prevented to super integrate in a single chip too many hardwired and micro controller bocks. Therefore, hardware designers had to carefully decide what to accelerate with respect to a software implementation, for example on 68020 micro controllers used in Apple computers. In fact, STV3200 needed only 115,000 transistors because of a deep hardware optimized design involving multiple technical dimensions. <br />
<br />
1) data precision of internal calculations, as minimized between 8, 12 to 16 bits <br />
<br />
2) datapath branches to compensate low precision compute of some part of the low bit depth circuitry to be compliant with IEEE 1180-1990, the IEEE Standard Specifications for the Implementations of 8x8 Inverse Discrete Cosine Transform, <br />
<br />
3) internal memory distribution, transposition [4.1][4.2] of read and write memory data access to avoid using costly additional SRAM blocks. <br />
<br />
These dimensions were met in the chip despite the need to pioneer the support of various block formats such as 16x16, 8x8, 4x4, 16x8, 8x4, 8x16, 4x8 that will be used many years later by MPEG-1,2, 4, H.264 and HEVC video standards. DCT coefficients were minimized to use only 12bits reducing furthermore internal memory footprint [4.6]. Internal data have been processed at 16 bits to minimize loss of precision instead of using 32 bits integer arithmetic. Integrated memory was only 4Kbits and be transposed [4.1] [4.2] in real time by the internal controller avoiding unnecessary duplications. Also, DCT separability to 1D was exploited to save silicon resources [4.7], [4.8], [4.9].<br />
<br />
Similar optimizations were applied to STi3220 motion estimator based on block matching between block of pixels; by limiting the search window to 256 positions the silicon complexity of the block matcher was reduced, shifting the random-access memory bottleneck into proper burst access to avoid the costly penalties of opening and closing memory pages (to access frame buffers) at pixel level with associated deadly loss of efficiency of the processor.<br />
<br />
The software computing obstacle had to be addressed in the most efficient manner.<br />
<br />
1) By hardwiring DCT and motion estimation/compensation processing functions, the most silicon area demanding function, hundreds of powerful micro controllers (such as Motorola 68020 or equivalent) were not anymore needed, while only an external 8bit controller using only 8Kbytes of ROM was capable to initiate decoding and searching operation once any picture was under decompression without being on the decoding critical path nor perform pixel level operations. That removed the need for any handshake between the external micro controller and the integrated circuits, avoiding hardware pipeline stalls that could result in picture freeze or annoying block artefacts affecting picture quality.<br />
<br />
Another challenge, as the silicon technology advanced for STi3240, STi3400, STi3500, STi3520, STi7000, STi5500 and successive derivative chips, was the memory bottleneck that became even more urgent to address due to the unified addressing space used by different accelerators. DRAM was costly and severely limited in space and bandwidth which in turn prevented the super integration since required to store I, P, B pictures and MPEG compressed bitstream. Decoding PAL and NTSC resolutions into only 16 Mbits of memory, to keep low the costs, implied several tricks to be implemented such as MPEG-2 B pictures decoding on the fly [4.4] and frame buffer compression [4.3] [4.5] [1.11] applied to both standard and high-definition decoders across the STi family. Novel memory reductions technique fixed the obstacle allowing MPEG SD decoding in only 8Mbits and HTDV in 32Mbits one of the most impressive achievement at that time.<br />
<br />
The energy consumption obstacle needed to be addressed to avoid power hungry systems. SoC optimizations allowed to keep the power consumption challenge between 0.5 and 1 W because higher power consumption would have reduced dramatically the reliability of the chips which were not using any heat sink other than a plastic package. This allowed to increase speed and functionality up to full High-Definition pictures within a single chip, also addressing the engine orchestrating obstacle due the on-chip CPU, video, audio and graphics concurrent executions and later on, super integrating also the micro controller (8 to 32bits), which resulted into dramatically minimized costs and greatly improved performances, as compared with competition multi-chip implementations.<br />
<br />
The STi family consisted of: STV3200 (DCT), STV3220 (Motion Estimator), STi3240, STi3400 (MPEG 1 video decoder), STi3500 (MPEG2 Video decoder), STi3520 (MPEG 2 audio and video decoder) and STi7000 (HD MPEG 2 video decoder and 3D graphics), STi5000 (integrating micro controllers) and many many others which we are not listing here for sake of brevity. <br />
<br />
Using low pin count and plastic packages without heat sinks mitigated the manufacturing cost obstacle and increased reliability of those chips that also necessitated from a simple 8-bit micro controller to a more complex 32bits CPU as companion first and then integrated in the SoC. <br />
<br />
In term of addressing the acceleration obstacle, by using such a deep hardware optimized design approach vs a full software one, the achieved performances were incomparable to state of art micro controllers such as 68020 which was unthinkable to be used due the excessive two digits number of them (to implement the decoding function) since 68020 was not optimized to process 60 or 120 million of pixels per second such the one required by high-definition MPEG 2 decoding. This need was further exacerbated later by the need to use on screen graphics to enhance used experience.<br />
<br />
Another obstacle to address was user experience which required high quality images produced with real time graphics processing. This was addressed by super integrating incrementally powerful image blitters, on screen display processor, 3D and 2D vector graphics engines to support user interfaces, internet browsers, gaming and 3D TV. ST was the 1st in bringing 3D graphics to the digital consumer market by implementing OpenGL-ES and OpenVG standards from the Khronos group.<br />
<br />
Figure 9 graphic images rendered by STi family to enhance user experience<br />
<br />
Organizational obstacles<br />
<br />
At the beginning in 1986 the digital multimedia applications and services were not existing because of the analog TV transmissions were dominating in everyone entertainment life, while the PC one was marginal for that domain. By consequence, the SGS-THOMSON management was reluctant to invest initially in a full generation of STi chips with an unpredictable return on investment a-head. The internal investments were purely R&D without any revenues, just losses in term of money discouraging further investments. Moreover, the seed cooperation between Rennes Electronics Laboratory, ENST Paris and Thomson Semiconductor under DAII sponsorship since 1986 first, then with Apple computer and RCA removed those barriers and was instrumental for SGS-Thomson to create a roadmap of chips, manufacture them and to boost the chip production motivating subsequent investments and multimedia applications and service flourishment.<br />
<br />
The architecture of the DCT chip was invented at ENST, [4.10] [4.11] [7.0], and the DCT industrial chip that was designed within the ENST laboratory (Alain Artieri spent a year in ENST team) using a specific CAD tool that was also developed within ENST, that made possible to generate this Hardware-Optimized solution. At that time, the head of the IC research group at ENST was Professor Francis Jutand, and Nicolas Demassieux was assistant professor. Nicolas Demassieux was personally participating to the MPEG1 (and later MPEG2) standardization efforts, and this work was fueled by EC-funded projects (such as the VADIS project). Both of Jutand and Demassieux came to SGS-Thomson, to convince the company managers to adopt DCT architecture and CAD tool. At that time, the internal ST design team was proposing 12 chips solutions, using gate-arrays. It took nearly a year to convince the manager of ST design team that Jutand and Demassieux had a credible solution, and a contract was signed between ENST and ST to a) licensing the intellectual property of two patents to ST, and 2) set-up a joint-design team that would design the DCT chip. Alain Artieri came for a year in the ENST team, and we designed together (with help of a couple of younger students) the layout of chip, while all the verifications (DRC, logical simulation....) were carried out in ST at Grenoble. Both Alain Artieri and Nicolas Demassieux designed the chip as equals in the collaboration.<br />
<br />
The ST team in Grenoble should be hailed for this adventure, and for being open-minded to change their "usual way of working" and accept this innovative idea of a joint academic/industry design team, to deliver this world's first STV3200 chip. This was a unique case (to our best knowledge) of an industrial chip being designed by a joint academic/industry team, through the collaboration between ENST and ST. Initial research work at ENST in 1986, described in [1.24]. [4.10] [4.11] patents granted to ENST in 1986 resulting from this research. Licensing and contractual agreement between ST and ENST during 1986 with final meeting to close the deal on Nov 12, 1986.<br />
<br />
A key management directive was to seek the market interest on those chips and an initial customer which was Apple Computer with whom SGS-Thomson specified the first MPEG1 ST3240 chip using available STV3200 implementing DCT. Secondly RCA, acquired by Thomson Consumer Electronics, was massively investing on Digital Satellite broadcast but its end-to-end system was lacking affordable decoding technologies. SGS-Thomson management decision was to take the risk on the decoder development without any commitment from RCA, with potential loss of development costs. Thanks to the deep hard work of SGS-Thomson a key engineer like Alain Artieri, it was released to RCA, one and half year ahead of C-Cube therefore being the first decoder being adopted into DirectTV digital multimedia broadcast.<br />
|a5=As reported into [1.9] many solutions for image and compression ICs were existing in 1992 however SGS-Thomson started since 1986. The ST innovations, which have been outlined in this IEEE Milestone proposal and which have created and provided significantly advancements in the field of digital multimedia, can be concisely summarized as follows:<br />
<br />
1) The silicon development started on 1986 between Rennes Electronics Laboratory, ENST Paris and Thomson Semiconductor under DAII sponsorship a-head of anybody else<br />
<br />
3) The 1st chip for mass production for forward and inverse DCT was STV3200 in 1988.<br />
<br />
4) The 1st chip for mass production for motion estimator was STV3220 in 1989.<br />
<br />
5) Their hardwired implementations replaced software solutions which needed hundreds of Motorola 68020 which were unable to achieve production and deployment into end user Set top boxes and digital TV.<br />
<br />
6) They incrementally implemented innovative techniques to reduce memory bandwidth such as block based efficient burst memory read and write, picture decoding on the fly, frame buffer compression to minimize external RAM needs and enable super integration of 1 bit transistor memory RAM cells in an on per requirement fashion.<br />
<br />
7) Gave the designer the freedom to use more advanced CMOS silicon lithography such as 0.5, 0.35um and successive in order to achieve super integration of more and more functionalities, to meet affordable mass production.<br />
<br />
8) Integrate more heterogeneous functions such as micro controller (8 bits, 32bits), audio decoding and 3D OpenGL-ES graphics<br />
<br />
9) System on Chip integration including faster processor cores (high instruction per cycles and frequency), caches (to handle code density and latency), memory controllers (for minimal latency communication with DDR), assisted by tool chains (with compilers adopted by a wide developer community) <br />
<br />
10) Addressing HDTV decoding, Video encoding and content Transcoding in real time<br />
<br />
11) Super integrating MPEG2 transport processing capabilities using STM32 bit microprocessor.<br />
<br />
12) Low dissipation <1W (figure 10) and high throughput efficiency<br />
<br />
Figure 10 Power dissipation minimized by STi family under 1W <br />
<br />
13) A continued investment on R&D and production started on 1986 till 2016 for 30 years of break-through products that shaped the digital multimedia domain (figure 11). <br />
<br />
Figure 11<br />
|references=1. TECHNICAL ARTICLES, CONFERENCE PAPERS & BOOKS<br />
<br />
[1.1] A. Artieri, S. Kritter, F. Jutand and N. Demassieux, "A one chip VLSI for real time two-dimensional discrete cosine transform," 1988., IEEE International Symposium on Circuits and Systems, 1988, pp. 701-704 vol.1, doi: 10.1109/ISCAS.1988.15022.<br />
<br />
[1.2] STV3200 DISCRETE COSINE TRANSFORM (DCT) Datasheet<br />
<br />
[1.3] A. Artieri and F. Jutand, "A versatile and powerful chip for real-time motion estimation," International Conference on Acoustics, Speech, and Signal Processing, 1989, pp. 2453-2456 vol.4, doi: 10.1109/ICASSP.1989.266964.<br />
<br />
[1.4] STi3220 MOTION ESTIMATOR PROCESSOR Datasheet<br />
<br />
[1.5] APPLICATION NOTE STi3220 MOTION ESTIMATION PROCESSOR CODEC<br />
<br />
[1.6] STi3400 MPEG/H.261 VIDEO DECODER DATASHEET<br />
<br />
[1.7] STi3500 MPEG2 CCIR 601H.261 VIDEO DECODER DATASHEET<br />
<br />
[1.8] Image and Video Compression standards: algorithm and architectures, Bhaskaran, Vasudev, Konstantinides, Konstantinos, ISBN 978-1-4615-6199-6, 1995<br />
<br />
[1.9] K. Konstantinides and V. Bhaskaran, "Monolithic architectures for image processing and compression," in IEEE Computer Graphics and Applications, vol. 12, no. 6, pp. 75-86, Nov. 1992, doi: 10.1109/38.163627.<br />
<br />
[1.10] A. Artieri and O. Colavin, "A chip set core for image compression," in IEEE Transactions on Consumer Electronics, vol. 36, no. 3, pp. 395-402, Aug. 1990, doi: 10.1109/30.103150.<br />
<br />
[1.11] A. Chimienti, M. Lucenteforte, D. Pau and R. Sannino, "A novel co-decoding scheme to reduce memory in MPEG-2 MP@ML decoder," 1998 URSI International Symposium on Signals, Systems, and Electronics. Conference Proceedings (Cat. No.98EX167), 1998, pp. 272-277, doi: 10.1109/ISSSE.1998.738080.<br />
<br />
[1.12] STi70000 press release<br />
<br />
[1.13] STi71000 datasheet<br />
<br />
[1.14] STi7200 datasheet<br />
<br />
[1.15] STi7108 datasheet<br />
<br />
[1.16] STi7108 processor with 3D graphics made public.<br />
<br />
[1.17] A chip set for MPEG-2 video encoding; Proceedings of the IEEE 1995 Custom Integrated Circuits Conference, 1995 <br />
<br />
[1.18] STi3240 MPEG1/H261 datasheet<br />
<br />
[1.19] STi3208 DCT chip datasheet<br />
<br />
[1.20] STi3520A MPEG2 chip datasheet<br />
<br />
[1.21] STi5600 MPEG2 chip datasheet<br />
<br />
[1.22] STi5610 MPEG2 chip datasheet<br />
<br />
[1.23] R. Bruni, A. Chimienti, M. Lucenteforte, D. Pau and R. Sannino, "A novel adaptive vector quantization method for memory reduction in MPEG-2 HDTV decoders," in IEEE Transactions on Consumer Electronics, vol. 44, no. 3, pp. 537-544, Aug. 1998, doi: 10.1109/30.713161.<br />
<br />
[1.24] F. Jutand, N. Demassieux, G. Concordel, J. Guichard and E. Cassimatis, "A single chip video rate 16×16 discrete cosine transform," ICASSP '86. IEEE International Conference on Acoustics, Speech, and Signal Processing, 1986, pp. 805-808, doi: 10.1109/ICASSP.1986.1169147.<br />
<br />
[1.25] N. Demassieux, G. Concordel, J. Durandeau and F. Jutand, "An optimized VLSI architecture for a multiformat discrete cosine transform," ICASSP '87. IEEE International Conference on Acoustics, Speech, and Signal Processing, 1987, pp. 547-550, doi: 10.1109/ICASSP.1987.1169851.<br />
<br />
[1.26] Tomasko, M., Buchhauser, D., Bushroe, M. et al. The Descent Imager/Spectral Radiometer (DISR) Experiment on the Huygens Entry Probe of Titan. Space Science Reviews 104, 469–551 (2002). https://doi.org/10.1023/A:1023632422098<br />
<br />
2. ONLINE INFORMATION AND CITATIONS<br />
<br />
[2.1] https://en.wikipedia.org/wiki/Motorola_68020 <br />
<br />
[2.2] https://techmonitor.ai/technology/sgs_thomson_debuts_one_chip_hdtv_system <br />
<br />
[2.3] Leonardo Chiariglione awards https://leonardo.chiariglione.org/public-life/awards/ <br />
<br />
[2.4] see pdf and https://www.eetimes.com/apis-help-stmicroelectronics-grow-set-top-box-business/# <br />
<br />
[2.5] see pdf and https://www.edn.com/sgs-thomson-microelectronics-named-number-one-mpeg-decoder-supplier-by-dataquest/ <br />
<br />
[2.6] see pdf and http://www.fundinguniverse.com/company-histories/stmicroelectronics-nv-history/ <br />
<br />
[2.7] https://books.google.it/books?id=C-bgBwAAQBAJ&pg=PA234&lpg=PA234&dq=stv3200+sgs-thomson&source=bl&ots=HrOQA0LEvS&sig=ACfU3U0vpZ7K5HJzJ1qJWjjlk4yfzPW82w&hl=it&sa=X&ved=2ahUKEwj2lZ2p35HwAhWBzKQKHVrmBBMQ6AEwEnoECBUQAw#v=onepage&q=stv3200%20sgs-thomson&f=false <br />
<br />
[2.8] http://www.quretec.com/u/vilo/edu/2002-03/Tekstialgoritmid_I/Loengud/Loeng7_Compression/www.faqs.org/faqs/compression-faq/part1/preamble.html<br />
<br />
[2.9] https://books.google.fr/books?id=UsH8CAAAQBAJ&lpg=PA501&ots=OJr_PN0LKo&dq=stv3200%20DCT&hl=fr&pg=PA501#v=onepage&q=stv3200%20DCT&f=false <br />
<br />
[2.10] http://ciclops.org/ir_index/208/In-Orbit?js=1 <br />
<br />
<br />
3. STMicroelectronics documents<br />
<br />
[3.1] De la Transformée en Cosinus Discrète aux Processeurs Applicatifs Multimédia, Alain Artiéri, Septembre 2007, STMicroelectronics presentation<br />
<br />
4. PATENTS<br />
<br />
[4.1] Integrated signal processing circuit for online and column summation of digital value matrices https://patents.google.com/patent/FR2608802B1/en?inventor=alain+artieri&oq=alain+artieri&sort=old <br />
<br />
[4.2] Transposition memory for data processing circuit https://patents.google.com/patent/FR2617621B1/en?inventor=alain+artieri&oq=alain+artieri&sort=old <br />
<br />
[4.3] Method and apparatus for addressing a memory area of an MPEG decoder4.6<br />
<br />
[4.4] publication number US6081298A MPEG decoder with reduced memory capacity<br />
<br />
[4.5] ITVA960016D0 Metodo di ricompressione e decompressione adpcm di un flusso di dati digitali costituente un segnale video digitale e stimatore https://patents.google.com/patent/ITVA960016D0/it?inventor=danilo+pau&oq=danilo+pau&sort=old<br />
<br />
[4.6] publication number 0 298 002 of 29.06.1988 Memoire de transposition pour circuit de traitement de donnes<br />
<br />
[4.7] publication number FR2649226A1 BREWING CIRCUIT OF DATA<br />
<br />
[4.8] publication number FR2650462B1 Device for converting a line scanning into a scanning in vertical saw teeth by bands; https://patents.google.com/patent/FR2650462B1/en?q=H04N3%2f30&inventor=alain+artieri&sort=old <br />
<br />
[4.9] publication number EP0368731B1 Process and circuit for image representation signal filtration<br />
<br />
[4.10] Circuit pour effectuer une transformation linéaire sur un signal numérique Patent issuer and number eu EP 0241352 A1 https://patents.google.com/patent/EP0241352A1<br />
<br />
[4.11] Additionneur binaire comportant un opérande fixé, et multiplieur binaire parallèle-série comprenant un tel additionneur Patent issuer and number eu EP 0262032 B1 https://patents.google.com/patent/EP0262032B1 <br />
<br />
5. Honors<br />
<br />
[5.1] Two European IT Prizes Awarded to STMicroelectronics<br />
<br />
6. MPEG mentions<br />
<br />
[6.1] Chiariglione and the birth of MPEG https://www.chiariglione.org/public-life/media/leonardo_ieee/prof.htm <br />
<br />
7. Letters of support<br />
<br />
[7.0] Endorsement by Leonardo Chiariglione, Nicolas Demassieux, Senior Vice President of<br />
Research, Orange, assistant professor at ENST (now Telecom ParisTech) mid 80s.<br />
<br />
[7.1] Endorsement by Leonardo Chiariglione, the father of MPEG<br />
<br />
[7.2] Endorsement by Prof Rocca, pioneer of motion estimation in 1969<br />
<br />
[7.3] Endorsement by Hisafumi Yamada, former Sony US TV CTO<br />
|submitted=Yes<br />
}}</div>Administrator1http://ieeemilestones.ethw.org/index.php?title=Milestone-Proposal:The_Birth_of_the_First_CT_Scanner&diff=10916Milestone-Proposal:The Birth of the First CT Scanner2021-04-27T19:45:22Z<p>Administrator1: </p>
<hr />
<div>{{Proposal<br />
|docketid=2020-02<br />
|litigation=No<br />
|more than 25 years=Yes<br />
|within fields of interest=Yes<br />
|benefit to humanity=Yes<br />
|regional importance=Yes<br />
|ou is paying=Yes<br />
|ou is arranging dedication=Yes<br />
|section is taking responsibility for plaque=Yes<br />
|a11=Yes<br />
|a3=1967-1975<br />
|a1=First Computerized Tomography (CT) X-ray Scanner, 1967-1975<br />
|plaque citation=On 1 October 1971, at the EMI Research Laboratories located on this site, an image of a patient’s brain was produced using the world’s first clinical X-ray Computerized Tomography scanner based on the patented inventions of Godfrey Hounsfield. The practical realization of high-resolution X-ray images of internal structures of the human body marked the beginning of a new era in clinical medicine.<br />
<br />
<b>Justification for including Godfrey Hounsfield's name in the Citation: </b><br />
<br />
The achievement being commemorated by the plaque is in respect of first human tissue image by a practical and reproducible CT scanner designed by Godfrey Hounsfield and built by EMI. Hounsfield's fundamental role was recognised by the award of the two US patents in his name, #3778614 and #4052619 cited below, as well as by a Nobel Prize. The patents were tested in the US courts and upheld. <br />
<br />
Whilst the Nobel prize was shared with Alan Cormack, Cormack worked independently in the United States and played no part in the EMI Labs achievement.<br />
|a2b=United Kingdom and Ireland<br />
|IEEE units paying={{IEEE Organizational Unit Paying<br />
|Unit=United Kingdom and Ireland<br />
|Senior officer name=Dr Mona Ghassemian<br />
|Senior officer email=mona.ghassemian@kcl.ac.uk<br />
}}<br />
|IEEE units arranging={{IEEE Organizational Unit Arranging<br />
|Unit=United Kingdom and Ireland Section<br />
|Senior officer name=Dr Mona Ghassemian<br />
|Senior officer email=mona.ghassemian@kcl.ac.uk<br />
}}<br />
|IEEE sections monitoring={{IEEE Section Monitoring<br />
|Section=United Kingdom and Ireland<br />
|Section chair name=Dr Mona Ghassemian<br />
|Section chair email=mona.ghassemian@j<br />
}}<br />
|Milestone proposers={{Milestone proposer<br />
|Proposer name=Charles W Turner<br />
|Proposer email=c.turner@ieee.org<br />
}}<br />
|a2a=150 Clayton Road Hayes Middlesex England GPS: 51.50556, -0.42659<br />
|a7=Jupiter House, former EMI Head Office<br />
|a8=No<br />
|mounting details=Exterior wall of Jupiter House<br />
|a9=Plaque will be permanently fixed to the wall.<br />
|a10=The Home Group, 2 Gosforth Park Way, Newcastle-on-Tyne, England<br />
|a4=The EMI CT Scanner was the first machine that used computerized tomography to produce X-Ray images of the internal organs of the human body, for example the brain.<br />
|a6=The scanning procedure required the acquisition of very large sets of data obtained by precision rotation of the X-Ray source and detector combination.<br />
The complete scan had to be accomplished within a practicable time frame.<br />
The incident X-Ray intensity had to be limited to safe levels for clinical applications.<br />
|a5=The EMI CT Scanner was the first clinical machine capable of producing high resolution images of X-ray attenuation, allowing depiction of the internal structures and organs of the human body.<br />
|references=Details of the supporting texts and other reference materials are provided separately via a number of attached files.<br />
Also attached are the permissions from the site owner and the UK & Ireland Section Chair<br />
<br />
*[[Media:Scan CT scan III.pdf]] - US Patent #3778614<br />
*[[Media:Scan CT scan V.pdf]] - US Patent #4052619<br />
*[[Media:Scan CT scan VIIa.pdf]] - Nobel Prize in Physiology or Medicine 1979 press release, part 1<br />
*[[Media:Scan CT scan VIIb.pdf]] - Nobel Prize in Physiology or Medicine 1979 press release, part 2]<br />
*[[Media:The invention of the CT scanner II.doc|The Invention of the CT scanner]]<br />
*[[Media:Patents by Inventor Godfrey Newbold Hounsfield.doc|Patents by Inventor Godfrey Newbold Hounsfield]]<br />
|supporting materials=All 11 attachments are being sent separately<br />
|submitted=Yes<br />
}}</div>Administrator1http://ieeemilestones.ethw.org/index.php?title=File:The_invention_of_the_CT_scanner_II.doc&diff=10915File:The invention of the CT scanner II.doc2021-04-27T19:43:57Z<p>Administrator1: </p>
<hr />
<div></div>Administrator1http://ieeemilestones.ethw.org/index.php?title=File:Patents_by_Inventor_Godfrey_Newbold_Hounsfield.doc&diff=10914File:Patents by Inventor Godfrey Newbold Hounsfield.doc2021-04-27T19:43:42Z<p>Administrator1: </p>
<hr />
<div></div>Administrator1http://ieeemilestones.ethw.org/index.php?title=File:US4052619(CT-Scan).pdf&diff=10877File:US4052619(CT-Scan).pdf2021-04-26T20:55:08Z<p>Administrator1: </p>
<hr />
<div></div>Administrator1http://ieeemilestones.ethw.org/index.php?title=File:US3778614(CT-Scan).pdf&diff=10876File:US3778614(CT-Scan).pdf2021-04-26T20:54:58Z<p>Administrator1: </p>
<hr />
<div></div>Administrator1http://ieeemilestones.ethw.org/index.php?title=Milestone-Proposal:Universal_Serial_Bus_(USB)&diff=10242Milestone-Proposal:Universal Serial Bus (USB)2021-02-26T17:20:31Z<p>Administrator1: </p>
<hr />
<div>{{Proposal<br />
|docketid=2020-07<br />
|litigation=No<br />
|more than 25 years=Yes<br />
|within fields of interest=Yes<br />
|benefit to humanity=Yes<br />
|regional importance=Yes<br />
|ou is paying=Yes<br />
|ou is arranging dedication=Yes<br />
|section is taking responsibility for plaque=Yes<br />
|a11=Yes<br />
|a3=1996<br />
|a1=Universal Serial Bus (USB), 1996<br />
|plaque citation=An industry consortium published the first Universal Serial Bus (USB) specification in January 1996. Intended to simplify attaching electronic devices to a computer, and initially directed to PCs, USB became a very successful industry-wide interface. Its versatile architecture supported new classes of devices, power delivery, battery charging, and high speed, while remaining low cost for home and business use. USB's cabling, connectors, and logo became recognizable worldwide.<br />
|a2b=Oregon<br />
|IEEE units paying={{IEEE Organizational Unit Paying<br />
|Unit=Oregon Section<br />
|Senior officer name=Paulo Vasconcelos<br />
|Senior officer email=paulo.vasconcelos@ieee.org<br />
}}<br />
|IEEE units arranging={{IEEE Organizational Unit Arranging<br />
|Unit=Oregon<br />
|Senior officer name=Paulo Vasconcelos<br />
|Senior officer email=paulo.vasconcelos@ieee.org<br />
}}<br />
|IEEE sections monitoring={{IEEE Section Monitoring<br />
|Section=Oregon<br />
|Section chair name=Paulo Vasconcelos<br />
|Section chair email=paulo.vasconcelos@ieee.org<br />
}}<br />
|Milestone proposers={{Milestone proposer<br />
|Proposer name=Brian A. Berg<br />
|Proposer email=b.berg@ieee.org<br />
}}<br />
|a2a=Intel Corporation, 2111 NE 25th Ave, Hillsboro, OR 97124 (Intel Jones Farm Campus) 45.543941 122.962248<br />
|a7=In the lobby of the Jones Farm Conference Center (JFCC) on the Intel Jones Farm Campus<br />
|a8=Yes<br />
|mounting details=On a wall in the lobby of the JFCC<br />
|a9=There is a security guard, and the lobby is open to the public during normal business hours<br />
|a10=Intel Corporation<br />
|a4=The key initial importance of USB was its impact on transforming the task of attaching and removing devices from computers from a process that required technical skills and patience into one that was as easy as inserting or removing a cable – a process dubbed as “Plug and Play.” USB thereby made computers more user friendly, whether it be at home, in an office setting, or in a data center. USB’s popularity led to other uses such charging batteries in cell phones and becoming the power connector for computers. As a result, USB has become ubiquitous on most computerized devices, and its logo and cabling are recognized worldwide.<br />
<br />
&#8226;<b><u><i>Expanding the capabilities PC-class computers was difficult before the mid-1990s</i></u></b><br><br />
Until the mid-1990s, it was difficult for anyone without some technical skills to significantly expand the capabilities of IBM PC-class computers. For the general consumer world, such a task was practical only for “hobbyists.” For the business world, an IT department whose staff could configure and support system reconfigurations or expansions was generally required.<br />
<br />
The means by which new hardware could be added to PCs was usually by using one or more of the following: the serial port, the parallel port (which sometimes adhered to the IEEE 488 standard), and an expansion board that was installed in an open slot in the computer’s internal motherboard. For example, adding a new device such as a digital scanner typically required opening up the PC and installing an expansion board that used either SCSI or some proprietary protocol. Such a task could include unscrewing and uncabling some existing components, manipulating jumpers and/or dip switches to configure DMA channels and IRQ request lines, and often much trial and error while having to power the PC on and off each time a change was made before the scanner could operate.<br />
<br />
Many of the problems encountered were due to the lack of standard practices amongst the many suppliers in the industry, and thus the difficulty of describing the necessary steps for adding the new hardware because of, for example, the configuration of devices already installed on the PC. As such, adding new hardware and returning the PC to a fully working condition was often a difficult task even for skilled hobbyists and professionals. The non-technical consumer public would either rely on staff at a computer store to undertake such a task, or they would not even consider adding a new device such as a scanner Retail computer superstore CompUSA reported that their product return rate for scanners was over 30%, and that the impact of these returns resulted in a net loss for the entirety of their scanner sales at that time.<br />
<br />
&#8226;<b><u><i>The Plug and Play Standard</i></u></b><br><br />
An effort called “Plug and Play” (abbreviated as PnP) began in the 1990s as part of an industry-wide effort to allow a PC to automatically self-configure both its hardware and software in order to accommodate the addition of a new device with little or no effort by the user. PnP was intended to be automatically invoked when new hardware was installed inside the PC, but also to accommodate “hot swapping” a device so as to not require the PC to first be powered off. Thus, the computer would automatically recognize any new device, load new software drivers if needed, and allow the newly-connected device to be usable.<br />
<br />
PnP was a collection of methods for determining and controlling system resource usage, and thereby required that a PC’s motherboard, system BIOS and peripherals all be PnP-compliant. A number of hardware and software companies developed the PnP standard for the control of all system resources so that changes could be dynamically performed when the computer was booted after a reconfiguration, as well as by plugging or unplugging a device while the computer was running.<br />
<br />
ISA PnP in 1993 defined hardware methods for detecting and configuring expansion cards, but typically didn’t expect those card to be re-configured during normal operation. A document titled “Plug and Play BIOS Specification Version 1.0A” was published on May 5, 1994 jointly by Compaq Computer Corp., Phoenix Technologies, Ltd. and Intel Corp. to define requirements for the system BIOS aspect of PnP, and soon thereafter Intel started shipping motherboards equipped with a PnP BIOS.<br />
<br />
Released in August 1995, Microsoft’s Windows 95 operating system’s major architectural changes as compared with its Windows 3.1 predecessor were critical to advancing PnP in the industry. Its System Registry worked with a comprehensive scheme of enumerating hardware at boot time, and the ability to dynamically allocate and deallocate resources as hardware was added or removed from a running PC. An essential Windows 95 PnP component was its "Add New Hardware" wizard which recognized when new hardware was attached, and which would guide the user through any steps necessary to allow its use.<br />
<br />
&#8226;<b><u><i>Intel initiated the efforts that led to USB’s creation</i></u></b><br><br />
Intel recognized that PnP needed a whole new interface protocol that would replace the PC’s parallel and serial interfaces with one that supported hot swapping. After initial work on a spec (initially called the “Serial Bus”) had been completed in early 1994, Jim Pappas (who had been working at Digital Equipment Corp., aka DEC) joined Intel and led the effort for this new bus. Intel invited key industry players to join a working group to further develop the spec, and their first meeting was held in May 1994 at Intel’s Jones Farm Campus in Hillsboro, OR. <br />
<br />
The attendees brainstormed about which direction to take and which technical skills to recruit for the effort. This meeting was the birth of what was eventually called the Universal Serial Bus, or USB. This effort resulted in seven companies working together to create USB Specification Revision 1.0 as released on Jan. 15, 1996: Compaq, Digital Equipment Corp. (DEC), the IBM PC Co., Intel, Microsoft, NEC and Northern Telecom (Nortel). USB embraced PnP's self identification and configuration technologies, and required that all USB devices had to be configured before they could be used.<br />
<br />
The introductory chapter of this first USB Specification states that the “motivation for the Universal Serial Bus comes from three interrelated considerations” which it describes as “Connection of the PC to the telephone” (due to “the merge of computing and communication” being “the basis for the next generation of productivity applications”), “Ease of use” (the difficulties resultant from the multiplicity of different means by which a device can be attached to a computer, including the serial/parallel ports discussed above, keyboard/mouse/joystick interfaces, and new interfaces created to accommodate new device types), and “Port expansion” (the limited number of ports in computers). Thus, the “lack of a bi-directional, low-cost, low-to-mid speed peripheral bus has held back the creative proliferation of peripherals.”<br />
<br />
&#8226;<b><u><i>The Importance of Intel’s Jones Farm Campus</i></u></b><br><br />
While the first USB specification was being created, most interactions with outside vendors took place during regularly-scheduled conference calls. Outside vendors such as Microsoft often came to meetings at Jones Farm, and face-to-face meetings were generally hosted by various companies elsewhere. However, the Jones Farm Campus became the "epicenter" of this endeavor as hardware and software was being developed and tested collaboratively.<br />
<br />
There is a glass conference room at the entrance of the Jones Farm 3 building (JF3) that was unique since it was accessible prior to reaching the security desk, and it had been a private conference room reserved for the most senior Intel executives. This room was allowed to be converted into a lab for a 3-month period, but it ended up being used for over 3 years by nearly every company working in the ever-growing USB industry. Dubbed the USB Product Integration Lab (PIL), it could be occupied by various companies 24 hours a day, even after the lobby was closed. As there were no USB devices, hubs or hosts in the early days, Intel created debug versions of these devices along with software drivers and test tools. All of the original furniture in the PIL was replaced with several lab benches, and every bench was filled with these debugging tools along with test equipment. Companies developing new USB products were able to use the PIL as a test and debug environment while working with Intel USB engineers in order to get USB signaling, packets and transactions operational. The companies using the PIL were often very secretive about the products that they had under development. Until at least 1996, most industry players involved in early development efforts used the PIL to debug their USB products before they went into production. Key to this effort was the availability of the first USB ICs from Intel in 1995.<br />
<br />
&#8226;<b><u><i>USB played an essential role in transitioning the PC into a consumer-level device</i></u></b><br><br />
The USB standard was created by the industry to allow the PC to expand beyond just business applications by enabling a consumer-friendly way to add devices to a computer, and also enabling new usage areas such as digital music and digital photography. Essential to USB was a standard connector on the exterior of the computer which allowed any type of USB device to be dynamically plugged into or unplugged from a running computer. Most computers included at least two such connectors, and a USB hub allowed multiple devices to be supported from a single USB connector.<br />
<br />
The fact that PnP was an essential aspect of the new Windows 95 architecture allowed the addition of support for USB by way of OEM Service Release (OSR) 2.1, which became available on August 27, 1997. Nearly every industry player, including Microsoft itself, used the USB PIL to debug and validate their products since Windows 95 was the first operating system to support the new USB standard.<br />
<br />
USB reached a critical turning point with the June 1998 release of Windows 98 because of its support of a draft version of the USB 1.1 spec. With Windows being the world’s most popular operating system, the number of USB devices on the market began to grow dramatically. In addtion, Apple's iMac (announced in May 1998 and released in August 1998) replaced its normal mouse and keyboard connectors with a pair of USB connectors.<br />
|a6=&#8226;<b><u><i>Technical Obstacles</i></u></b><br><br />
USB’s most significant technical challenge was containing costs. The USB design target included the mouse, the single most common pointing device at the time. Microsoft disclosed that the entire electronics budget for their optical mouse was only 50 cents. Using the mouse as the baseline, this design target set up a series of challenges regarding how to keep the design simple and inexpensive, while still allowing it to expand into areas such as imaging, storage, and synchronous applications such as music and digital telephony.<br />
<br />
A second significant technical obstacle arose due to the desire to minimize cost. The challenge was how to accomplish all the desired communication and control functionalities using only a single differential signaling pair - essentially one logical wire. In comparison, other popular cabled connections of the time used many wires, with wires dedicated to special signals such as interrupts.<br />
<br />
&#8226;<b><u><i>Broad Acceptance Obstacle</i></u></b><br><br />
USB faced a critical obstacle for its acceptance and success in the marketplace. The industry recognized the need for a simplified low-cost interface that used a single connector to support a variety of hot-swappable devices, and USB’s main competition in achieving this was IEEE 1394/FireWire and ACCESS.bus:<br><br />
• <u>IEEE 1394/FireWire:</u><br><br />
&nbsp;&nbsp;o Like USB, it included both power and data on its cabling, but 1394 provided more power<br><br />
&nbsp;&nbsp;o Like USB, it supported hot-swapping (and hence could potentially be plug-and-play)<br><br />
&nbsp;&nbsp;o USB had significantly lower cost than 1394 because of its simplicity (use of a host master) as compared with 1394’s symmetric and more complex peer-to-peer architecture, as well as because its initial design was as a lower-performance interface than 1394<br><br />
&nbsp;&nbsp;o While Steve Jobs was receiving a royalty from PC OEMs of $1 for each 1394 port, Intel was adding USB to its own processor chipset. Since the resultant PC OEM cost of adding USB was thus little more than the cost of adding a pair of USB connectors, the incentive to include 1394 ports in PCs was greatly diminished.<br><br />
&nbsp;&nbsp;o As a result, USB connectors were included on most new PCs near the time of USB’s 1996 introduction, and USB was supported in Microsoft Windows in 1997<br><br />
&nbsp;&nbsp;o USB thus marginalized 1394 to a higher-priced echelon of the consumer electronics market<br><br />
• <u>Apple Desktop Bus (ADB):</u><br><br />
&nbsp;&nbsp;o Proprietary to Apple, and so never a direct USB competitor<br><br />
&nbsp;&nbsp;o Only ever used for low-speed devices such as keyboards and mice<br><br />
&nbsp;&nbsp;o Did not support hot swapping<br><br />
&nbsp;&nbsp;o Introduced on the Apple IIGS in 1986, and used on Apple products until the early 2000s<br><br />
&nbsp;&nbsp;o Used on some NeXT computers, and some third-party computers<br><br />
&nbsp;&nbsp;o Apple replaced ADB with USB starting with the 1998 iMac (which also included FireWire)<br><br />
• <u>ACCESS.bus (A.b)</u><br><br />
&nbsp;&nbsp;o Created by Philips and DEC for the PC as a way to reproduce much of what ADB offered<br><br />
&nbsp;&nbsp;o Supported hot swapping, but its 10 kbit/sec and 100 kbit/sec speeds were much slower than USB’s slowest speeds of 1.5 Mbits/sec and 12 Mbits/sec<br><br />
&nbsp;&nbsp;o ACCESS.bus Industry Group (ABIG) was formed in 1993, and included Microsoft and DEC<br><br />
&nbsp;&nbsp;o Interest waned with Intel’s backing of USB, leaving Philips as the prime supporter<br><br />
&nbsp;&nbsp;o ACCESS.bus thus never achieved widespread use<br><br />
<br />
&#8226;<b><u><i>Political Obstacle</i></u></b><br><br />
A “political” obstacle occurred once it was obvious that USB had broad industry support. A wide variety of requests started to arrive from adjacent markets that wanted to utilize the ubiquity and low cost expected from USB, including numerous requests for additional features which would have expanded the design of USB well beyond its original simple objectives. Examples include (1) fully symmetric and autonomous operation so that devices could communicate even if the PC was powered off, (2) long range cable lengths of up to 1 km, and (3) waterproof connectors for underwater dive computers.<br />
|a5=&#8226;<b><u><i>USB’s Asymmetric Design Allowed for Simplicity and Lower Cost</i></u></b><br><br />
USB was based on a strategic design choice of being asymmetric to take advantage of the fact that the host side interface would have the extensive resources available to a full PC, thus allowing design choices for the device side of the wire to be relatively simple. This decision was hugely beneficial as it (1) allowed the capabilities of a USB device to range from ultra-simplistic to highly sophisticated, (2) differentiated USB from the symmetric design and resultant higher cost of IEEE 1394/FireWire, and (3) led to a broad range of types of USB devices being possible, and which was ever-expanding.<br />
<br />
&#8226;<b><u><i>USB’s Inclusion of Power in Its Cabling</i></u></b><br><br />
The early decision to supply power to attached devices was quite controversial as no widely-used computer interface provided power at that time. The main reason for this was to accommodate devices such as keyboards and mice, which could not have a separate power supply connection. Other devices were also envisioned that could be fully powered from the bus.<br />
<br />
A big surprise was when Logitech completely re-engineered its prototype portable sheet scanner (including the use of new motors) to operate within USB’s 2.5 Watt limit. The inclusion of power often precluded the need for a wall plug power adapter (often called a “wall wart”), and this also had a huge positive impact since it allowed a single cable to attach a wide variety of devices to a PC.<br />
<br />
&#8226;<b><u><i>USB’s Inclusion of Power Allowed it to Eventually Function as a Charger</i></u></b><br><br />
USB’s inclusion of power proved to be hugely beneficial to USB’s success in ways that were far beyond what anyone had envisioned in the mid-1990s. Starting in around 2006, a number of cell phone suppliers (most notably Motorola and Nokia) developed an ancillary specification for the Micro-USB connector specification that would better serve the mobile phone market. In around 2007, Qualcomm and Nokia led an effort to develop the Battery Charging Specification to enable increasing the 5-volt supply current beyond 500 mA when used for mobile phone charging. Thus, USB ports could offer up to 1.5A (7.5 Watts) when enabled for charging using a standardized discovery technique based on the termination of the USB 2.0 data bus pins, and this scheme served the mobile phone industry for several years.<br />
<br />
Starting in 2012, competitive pressures in the explosively expanding cell phone market led to interoperability issues with the standard USB Micro-B connector as proprietary charging techniques that pushed the power boundaries beyond the USB standard's 5V @ 1.5A limitation came into use. One example is Qualcomm’s Quick Charge (QC) technology.<br />
<br />
With the formal introduction of the USB Type-C connector in 2014, and based on the methodologies of the 2012 USB Power Delivery standard, a fully standardized USB charging solution tailored to a broad range of applications became available, and these standards have matured with the marketplace. The USB 3.1 standard allowed USB to deliver up to 100 Watts of power, and USB 3.2 standard included the previously standardized Type-C connector.<br />
<br />
&#8226;<b><u><i>USB’s Simple Design Was Essential to Its Success</i></u></b><br><br />
The USB standard purposefully defined several standard device classes including mass storage, audio, video and communication. These device classes allowed OS vendors to provide standardized device drivers, and avoided having every device vendor provide their own driver. This further reduced errors in the field due to incorrectly implemented device drivers, and these have proved adequate to support a broad range of device types. It was felt that if USB was allowed to increase in complexity, a lack of focus would prevent it from remaining low-cost and achieving widespread usage. As such, the standard was created with the intent that the feature set and cost were in line with the ability of computer manufacturers to provide USB in every platform, and as part of every base configuration – and this intent has been proven in the marketplace.<br />
<br />
This simple design allowed USB to address its targeted applications (which initially were peripherals attached to PC-class computers), and also allowed the vast majority of other device types to find a way to make USB work. Indeed, the different usages of USB have been ever-increasing over the years. Thus, while initially created to ease the difficulties of connecting new hardware to PC-class computers, USB’s simple design philosophy has led to its adoption throughout the computer, consumer electronics and mobile communications industries, into automobiles and industrial automation applications, and for power applications such as recharging batteries as well as providing primary power to computers and many other kinds of devices.<br />
<br />
&#8226;<b><u><i>USB’s Universality</i></u></b><br><br />
There is no other computerized interface in the world that has had anything approaching USB’s widespread acceptance – it is truly ubiquitous, and it has seen a continual increase in usage in an ever-broadening range of product categories since its 1996 introduction. In 2006 alone, over 2 billion USB devices were shipped.<br />
<br />
&#8226;<b><u><i>USB Implementers Forum (USB-IF)</i></u></b><br><br />
Much of USB’s success is due to its having been designed by a broad industry coalition. As key players in that coalition were writing the USB 1.0 Specification, they created the USB Implementers Forum (USB-IF) in 1995 as a nonprofit organization, and whose main activities have been the promotion and marketing of USB, the creation and maintenance of USB ancillary standard specifications, and running a compliance program to ensure adherence to these specifications. Devices proven to comply with the USB-IF certified testing protocol can be sold with a USB-certified logo.<br />
<br />
In addition, the USB “trident” logo was created at the time of the USB 1.0 Specification. The inclusion of this logo on cabling and adjacent to connectors has led to it becoming USB’s most universally recognized symbol. The different shapes at the tips of the trident’s three prongs represent the multiple device types able to be supported by USB, and on a single port.<br />
<br />
&#8226;<b><u><i>USB Timeline</i></u></b><br><br />
• <b>May 1994</b>: Intel invited representatives from major industry players to a meeting at the Intel Jones Farm campus to discuss “Serial Bus,” a new serial protocol that Intel proposed to replace the antiquated serial and parallel interfaces that were then standard on PC class computers. This bus was eventually given the name Universal Serial Bus, or USB.<br><br />
• <b>Sept. 1995</b>: USB was introduced to an industry gathering of about 700 at the Fairmont Hotel in San Jose, CA. When Jim Pappas was introduced, he walked from the back of the room to the stage while dragging behind him a large swath of cables with mice, keyboards and other peripherals attached. He started his keynote address by saying that “all of this can be replaced by just one of these” while holding up a single USB Type A connector. By the time of this event, 160 companies had registered for USB Vendor IDs.<br><br />
• <b>Jan. 15, 1996</b>: Revision 1.0 of the USB Specification as created by seven key industry players (Compaq, Digital Equipment Corporation (DEC), the IBM PC Co., Intel, Microsoft, NEC and Northern Telecom (Nortel)) was made public. It supported speeds of 1.5 Mbits/sec and 12 Mbits/sec.<br><br />
• <b>August 27, 1997</b>: Windows 95 OEM Service Release (OSR) 2.1 was released with support for USB, and over 1100 companies had registered for USB Vendor IDs around this timeframe.<br><br />
• <b>June 25, 1998</b>: Windows 98 was released with support for a draft version of the USB 1.1 spec.<br><br />
• <b>August 15, 1998</b>: the Apple iMac G3 was released without an integrated floppy drive, but with USB 1.1 support for a pair of USB connectors able to support devices including a keyboard and mouse, and with industry support for a floppy drive.<br><br />
• <b>Sept. 23, 1998</b>: Revision 1.1 of the USB Specification was released with various embellishments and clarifications.<br><br />
• <b>April 27, 2000</b>: Revision 2.0 of the USB Specification was released, which added high-speed mode @ 480 Mbits/sec (a 40x improvement).<br><br />
• <b>Nov. 12, 2008</b>: Revision 3.0 of the USB Specification was released, which added SuperSpeed mode @ 5 Gbits/sec (an over 10x improvement).<br><br />
• <b>July 26, 2013</b>: Revision 3.1 of the USB Specification was released, which added SuperSpeedPlus @ 10 Gbits/sec (a 2x improvement), and support for up to 100 Watts of power.<br><br />
• <b>Sept. 22, 2017</b>: Revision USB 3.2 of the USB Specification was released, which added a 2nd data lane for a 2x improvement, and the Type C connector.<br><br />
• <b>August 29, 2019</b>: the USB4 Specification was released, which expanded data transfer modes, including tunneling.<br><br />
|supporting materials=*[[media:PnP-BIOS-Specification-V1.0A.pdf]]<br />
*USB 1.0: https://fl.hw.cz/docs/usb/usb10doc.pdf<br />
*USB 1.1: http://esd.cs.ucr.edu/webres/usb11.pdf / http://www.13thmonkey.org/documentation/USB/usb11.pdf<br />
*USB 2.0: https://www.usb.org/document-library/usb-20-specification<br />
*https://www.intel.com/content/www/us/en/standards/usb-two-decades-of-plug-and-play-article.html<br />
|submitted=No<br />
}}</div>Administrator1http://ieeemilestones.ethw.org/index.php?title=Milestone-Proposal:Universal_Serial_Bus_(USB)&diff=10241Milestone-Proposal:Universal Serial Bus (USB)2021-02-26T17:18:55Z<p>Administrator1: </p>
<hr />
<div>{{Proposal<br />
|docketid=2020-07<br />
|litigation=No<br />
|more than 25 years=Yes<br />
|within fields of interest=Yes<br />
|benefit to humanity=Yes<br />
|regional importance=Yes<br />
|ou is paying=Yes<br />
|ou is arranging dedication=Yes<br />
|section is taking responsibility for plaque=Yes<br />
|a11=Yes<br />
|a3=1996<br />
|a1=Universal Serial Bus (USB), 1996<br />
|plaque citation=An industry consortium published the first Universal Serial Bus (USB) specification in January 1996. Intended to simplify attaching electronic devices to a computer, and initially directed to PCs, USB became a very successful industry-wide interface. Its versatile architecture supported new classes of devices, power delivery, battery charging, and high speed, while remaining low cost for home and business use. USB's cabling, connectors, and logo became recognizable worldwide.<br />
|a2b=Oregon<br />
|IEEE units paying={{IEEE Organizational Unit Paying<br />
|Unit=Oregon Section<br />
|Senior officer name=Paulo Vasconcelos<br />
|Senior officer email=paulo.vasconcelos@ieee.org<br />
}}<br />
|IEEE units arranging={{IEEE Organizational Unit Arranging<br />
|Unit=Oregon<br />
|Senior officer name=Paulo Vasconcelos<br />
|Senior officer email=paulo.vasconcelos@ieee.org<br />
}}<br />
|IEEE sections monitoring={{IEEE Section Monitoring<br />
|Section=Oregon<br />
|Section chair name=Paulo Vasconcelos<br />
|Section chair email=paulo.vasconcelos@ieee.org<br />
}}<br />
|Milestone proposers={{Milestone proposer<br />
|Proposer name=Brian A. Berg<br />
|Proposer email=b.berg@ieee.org<br />
}}<br />
|a2a=Intel Corporation, 2111 NE 25th Ave, Hillsboro, OR 97124 (Intel Jones Farm Campus) 45.543941 122.962248<br />
|a7=In the lobby of the Jones Farm Conference Center (JFCC) on the Intel Jones Farm Campus<br />
|a8=Yes<br />
|mounting details=On a wall in the lobby of the JFCC<br />
|a9=There is a security guard, and the lobby is open to the public during normal business hours<br />
|a10=Intel Corporation<br />
|a4=The key initial importance of USB was its impact on transforming the task of attaching and removing devices from computers from a process that required technical skills and patience into one that was as easy as inserting or removing a cable – a process dubbed as “Plug and Play.” USB thereby made computers more user friendly, whether it be at home, in an office setting, or in a data center. USB’s popularity led to other uses such charging batteries in cell phones and becoming the power connector for computers. As a result, USB has become ubiquitous on most computerized devices, and its logo and cabling are recognized worldwide.<br />
<br />
&#8226;<b><u><i>Expanding the capabilities PC-class computers was difficult before the mid-1990s</i></u></b><br><br />
Until the mid-1990s, it was difficult for anyone without some technical skills to significantly expand the capabilities of IBM PC-class computers. For the general consumer world, such a task was practical only for “hobbyists.” For the business world, an IT department whose staff could configure and support system reconfigurations or expansions was generally required.<br />
<br />
The means by which new hardware could be added to PCs was usually by using one or more of the following: the serial port, the parallel port (which sometimes adhered to the IEEE 488 standard), and an expansion board that was installed in an open slot in the computer’s internal motherboard. For example, adding a new device such as a digital scanner typically required opening up the PC and installing an expansion board that used either SCSI or some proprietary protocol. Such a task could include unscrewing and uncabling some existing components, manipulating jumpers and/or dip switches to configure DMA channels and IRQ request lines, and often much trial and error while having to power the PC on and off each time a change was made before the scanner could operate.<br />
<br />
Many of the problems encountered were due to the lack of standard practices amongst the many suppliers in the industry, and thus the difficulty of describing the necessary steps for adding the new hardware because of, for example, the configuration of devices already installed on the PC. As such, adding new hardware and returning the PC to a fully working condition was often a difficult task even for skilled hobbyists and professionals. The non-technical consumer public would either rely on staff at a computer store to undertake such a task, or they would not even consider adding a new device such as a scanner Retail computer superstore CompUSA reported that their product return rate for scanners was over 30%, and that the impact of these returns resulted in a net loss for the entirety of their scanner sales at that time.<br />
<br />
&#8226;<b><u><i>The Plug and Play Standard</i></u></b><br><br />
An effort called “Plug and Play” (abbreviated as PnP) began in the 1990s as part of an industry-wide effort to allow a PC to automatically self-configure both its hardware and software in order to accommodate the addition of a new device with little or no effort by the user. PnP was intended to be automatically invoked when new hardware was installed inside the PC, but also to accommodate “hot swapping” a device so as to not require the PC to first be powered off. Thus, the computer would automatically recognize any new device, load new software drivers if needed, and allow the newly-connected device to be usable.<br />
<br />
PnP was a collection of methods for determining and controlling system resource usage, and thereby required that a PC’s motherboard, system BIOS and peripherals all be PnP-compliant. A number of hardware and software companies developed the PnP standard for the control of all system resources so that changes could be dynamically performed when the computer was booted after a reconfiguration, as well as by plugging or unplugging a device while the computer was running.<br />
<br />
ISA PnP in 1993 defined hardware methods for detecting and configuring expansion cards, but typically didn’t expect those card to be re-configured during normal operation. A document titled “Plug and Play BIOS Specification Version 1.0A” was published on May 5, 1994 jointly by Compaq Computer Corp., Phoenix Technologies, Ltd. and Intel Corp. to define requirements for the system BIOS aspect of PnP, and soon thereafter Intel started shipping motherboards equipped with a PnP BIOS.<br />
<br />
Released in August 1995, Microsoft’s Windows 95 operating system’s major architectural changes as compared with its Windows 3.1 predecessor were critical to advancing PnP in the industry. Its System Registry worked with a comprehensive scheme of enumerating hardware at boot time, and the ability to dynamically allocate and deallocate resources as hardware was added or removed from a running PC. An essential Windows 95 PnP component was its "Add New Hardware" wizard which recognized when new hardware was attached, and which would guide the user through any steps necessary to allow its use.<br />
<br />
&#8226;<b><u><i>Intel initiated the efforts that led to USB’s creation</i></u></b><br><br />
Intel recognized that PnP needed a whole new interface protocol that would replace the PC’s parallel and serial interfaces with one that supported hot swapping. After initial work on a spec (initially called the “Serial Bus”) had been completed in early 1994, Jim Pappas (who had been working at Digital Equipment Corp., aka DEC) joined Intel and led the effort for this new bus. Intel invited key industry players to join a working group to further develop the spec, and their first meeting was held in May 1994 at Intel’s Jones Farm Campus in Hillsboro, OR. <br />
<br />
The attendees brainstormed about which direction to take and which technical skills to recruit for the effort. This meeting was the birth of what was eventually called the Universal Serial Bus, or USB. This effort resulted in seven companies working together to create USB Specification Revision 1.0 as released on Jan. 15, 1996: Compaq, Digital Equipment Corp. (DEC), the IBM PC Co., Intel, Microsoft, NEC and Northern Telecom (Nortel). USB embraced PnP's self identification and configuration technologies, and required that all USB devices had to be configured before they could be used.<br />
<br />
The introductory chapter of this first USB Specification states that the “motivation for the Universal Serial Bus comes from three interrelated considerations” which it describes as “Connection of the PC to the telephone” (due to “the merge of computing and communication” being “the basis for the next generation of productivity applications”), “Ease of use” (the difficulties resultant from the multiplicity of different means by which a device can be attached to a computer, including the serial/parallel ports discussed above, keyboard/mouse/joystick interfaces, and new interfaces created to accommodate new device types), and “Port expansion” (the limited number of ports in computers). Thus, the “lack of a bi-directional, low-cost, low-to-mid speed peripheral bus has held back the creative proliferation of peripherals.”<br />
<br />
&#8226;<b><u><i>The Importance of Intel’s Jones Farm Campus</i></u></b><br><br />
While the first USB specification was being created, most interactions with outside vendors took place during regularly-scheduled conference calls. Outside vendors such as Microsoft often came to meetings at Jones Farm, and face-to-face meetings were generally hosted by various companies elsewhere. However, the Jones Farm Campus became the "epicenter" of this endeavor as hardware and software was being developed and tested collaboratively.<br />
<br />
There is a glass conference room at the entrance of the Jones Farm 3 building (JF3) that was unique since it was accessible prior to reaching the security desk, and it had been a private conference room reserved for the most senior Intel executives. This room was allowed to be converted into a lab for a 3-month period, but it ended up being used for over 3 years by nearly every company working in the ever-growing USB industry. Dubbed the USB Product Integration Lab (PIL), it could be occupied by various companies 24 hours a day, even after the lobby was closed. As there were no USB devices, hubs or hosts in the early days, Intel created debug versions of these devices along with software drivers and test tools. All of the original furniture in the PIL was replaced with several lab benches, and every bench was filled with these debugging tools along with test equipment. Companies developing new USB products were able to use the PIL as a test and debug environment while working with Intel USB engineers in order to get USB signaling, packets and transactions operational. The companies using the PIL were often very secretive about the products that they had under development. Until at least 1996, most industry players involved in early development efforts used the PIL to debug their USB products before they went into production. Key to this effort was the availability of the first USB ICs from Intel in 1995.<br />
<br />
&#8226;<b><u><i>USB played an essential role in transitioning the PC into a consumer-level device</i></u></b><br><br />
The USB standard was created by the industry to allow the PC to expand beyond just business applications by enabling a consumer-friendly way to add devices to a computer, and also enabling new usage areas such as digital music and digital photography. Essential to USB was a standard connector on the exterior of the computer which allowed any type of USB device to be dynamically plugged into or unplugged from a running computer. Most computers included at least two such connectors, and a USB hub allowed multiple devices to be supported from a single USB connector.<br />
<br />
The fact that PnP was an essential aspect of the new Windows 95 architecture allowed the addition of support for USB by way of OEM Service Release (OSR) 2.1, which became available on August 27, 1997. Nearly every industry player, including Microsoft itself, used the USB PIL to debug and validate their products since Windows 95 was the first operating system to support the new USB standard.<br />
<br />
USB reached a critical turning point with the June 1998 release of Windows 98 because of its support of a draft version of the USB 1.1 spec. With Windows being the world’s most popular operating system, the number of USB devices on the market began to grow dramatically. In addtion, Apple's iMac (announced in May 1998 and released in August 1998) replaced its normal mouse and keyboard connectors with a pair of USB connectors.<br />
|a6=&#8226;<b><u><i>Technical Obstacles</i></u></b><br><br />
USB’s most significant technical challenge was containing costs. The USB design target included the mouse, the single most common pointing device at the time. Microsoft disclosed that the entire electronics budget for their optical mouse was only 50 cents. Using the mouse as the baseline, this design target set up a series of challenges regarding how to keep the design simple and inexpensive, while still allowing it to expand into areas such as imaging, storage, and synchronous applications such as music and digital telephony.<br />
<br />
A second significant technical obstacle arose due to the desire to minimize cost. The challenge was how to accomplish all the desired communication and control functionalities using only a single differential signaling pair - essentially one logical wire. In comparison, other popular cabled connections of the time used many wires, with wires dedicated to special signals such as interrupts.<br />
<br />
&#8226;<b><u><i>Broad Acceptance Obstacle</i></u></b><br><br />
USB faced a critical obstacle for its acceptance and success in the marketplace. The industry recognized the need for a simplified low-cost interface that used a single connector to support a variety of hot-swappable devices, and USB’s main competition in achieving this was IEEE 1394/FireWire and ACCESS.bus:<br><br />
• <u>IEEE 1394/FireWire:</u><br><br />
&nbsp;&nbsp;o Like USB, it included both power and data on its cabling, but 1394 provided more power<br><br />
&nbsp;&nbsp;o Like USB, it supported hot-swapping (and hence could potentially be plug-and-play)<br><br />
&nbsp;&nbsp;o USB had significantly lower cost than 1394 because of its simplicity (use of a host master) as compared with 1394’s symmetric and more complex peer-to-peer architecture, as well as because its initial design was as a lower-performance interface than 1394<br><br />
&nbsp;&nbsp;o While Steve Jobs was receiving a royalty from PC OEMs of $1 for each 1394 port, Intel was adding USB to its own processor chipset. Since the resultant PC OEM cost of adding USB was thus little more than the cost of adding a pair of USB connectors, the incentive to include 1394 ports in PCs was greatly diminished.<br><br />
&nbsp;&nbsp;o As a result, USB connectors were included on most new PCs near the time of USB’s 1996 introduction, and USB was supported in Microsoft Windows in 1997<br><br />
&nbsp;&nbsp;o USB thus marginalized 1394 to a higher-priced echelon of the consumer electronics market<br><br />
• <u>Apple Desktop Bus (ADB):</u><br><br />
&nbsp;&nbsp;o Proprietary to Apple, and so never a direct USB competitor<br><br />
&nbsp;&nbsp;o Only ever used for low-speed devices such as keyboards and mice<br><br />
&nbsp;&nbsp;o Did not support hot swapping<br><br />
&nbsp;&nbsp;o Introduced on the Apple IIGS in 1986, and used on Apple products until the early 2000s<br><br />
&nbsp;&nbsp;o Used on some NeXT computers, and some third-party computers<br><br />
&nbsp;&nbsp;o Apple replaced ADB with USB starting with the 1998 iMac (which also included FireWire)<br><br />
• <u>ACCESS.bus (A.b)</u><br><br />
&nbsp;&nbsp;o Created by Philips and DEC for the PC as a way to reproduce much of what ADB offered<br><br />
&nbsp;&nbsp;o Supported hot swapping, but its 10 kbit/sec and 100 kbit/sec speeds were much slower than USB’s slowest speeds of 1.5 Mbits/sec and 12 Mbits/sec<br><br />
&nbsp;&nbsp;o ACCESS.bus Industry Group (ABIG) was formed in 1993, and included Microsoft and DEC<br><br />
&nbsp;&nbsp;o Interest waned with Intel’s backing of USB, leaving Philips as the prime supporter<br><br />
&nbsp;&nbsp;o ACCESS.bus thus never achieved widespread use<br><br />
<br />
&#8226;<b><u><i>Political Obstacle</i></u></b><br><br />
A “political” obstacle occurred once it was obvious that USB had broad industry support. A wide variety of requests started to arrive from adjacent markets that wanted to utilize the ubiquity and low cost expected from USB, including numerous requests for additional features which would have expanded the design of USB well beyond its original simple objectives. Examples include (1) fully symmetric and autonomous operation so that devices could communicate even if the PC was powered off, (2) long range cable lengths of up to 1 km, and (3) waterproof connectors for underwater dive computers.<br />
|a5=&#8226;<b><u><i>USB’s Asymmetric Design Allowed for Simplicity and Lower Cost</i></u></b><br><br />
USB was based on a strategic design choice of being asymmetric to take advantage of the fact that the host side interface would have the extensive resources available to a full PC, thus allowing design choices for the device side of the wire to be relatively simple. This decision was hugely beneficial as it (1) allowed the capabilities of a USB device to range from ultra-simplistic to highly sophisticated, (2) differentiated USB from the symmetric design and resultant higher cost of IEEE 1394/FireWire, and (3) led to a broad range of types of USB devices being possible, and which was ever-expanding.<br />
<br />
&#8226;<b><u><i>USB’s Inclusion of Power in Its Cabling</i></u></b><br><br />
The early decision to supply power to attached devices was quite controversial as no widely-used computer interface provided power at that time. The main reason for this was to accommodate devices such as keyboards and mice, which could not have a separate power supply connection. Other devices were also envisioned that could be fully powered from the bus.<br />
<br />
A big surprise was when Logitech completely re-engineered its prototype portable sheet scanner (including the use of new motors) to operate within USB’s 2.5 Watt limit. The inclusion of power often precluded the need for a wall plug power adapter (often called a “wall wart”), and this also had a huge positive impact since it allowed a single cable to attach a wide variety of devices to a PC.<br />
<br />
&#8226;<b><u><i>USB’s Inclusion of Power Allowed it to Eventually Function as a Charger</i></u></b><br><br />
USB’s inclusion of power proved to be hugely beneficial to USB’s success in ways that were far beyond what anyone had envisioned in the mid-1990s. Starting in around 2006, a number of cell phone suppliers (most notably Motorola and Nokia) developed an ancillary specification for the Micro-USB connector specification that would better serve the mobile phone market. In around 2007, Qualcomm and Nokia led an effort to develop the Battery Charging Specification to enable increasing the 5-volt supply current beyond 500 mA when used for mobile phone charging. Thus, USB ports could offer up to 1.5A (7.5 Watts) when enabled for charging using a standardized discovery technique based on the termination of the USB 2.0 data bus pins, and this scheme served the mobile phone industry for several years.<br />
<br />
Starting in 2012, competitive pressures in the explosively expanding cell phone market led to interoperability issues with the standard USB Micro-B connector as proprietary charging techniques that pushed the power boundaries beyond the USB standard's 5V @ 1.5A limitation came into use. One example is Qualcomm’s Quick Charge (QC) technology.<br />
<br />
With the formal introduction of the USB Type-C connector in 2014, and based on the methodologies of the 2012 USB Power Delivery standard, a fully standardized USB charging solution tailored to a broad range of applications became available, and these standards have matured with the marketplace. The USB 3.1 standard allowed USB to deliver up to 100 Watts of power, and USB 3.2 standard included the previously standardized Type-C connector.<br />
<br />
&#8226;<b><u><i>USB’s Simple Design Was Essential to Its Success</i></u></b><br><br />
The USB standard purposefully defined several standard device classes including mass storage, audio, video and communication. These device classes allowed OS vendors to provide standardized device drivers, and avoided having every device vendor provide their own driver. This further reduced errors in the field due to incorrectly implemented device drivers, and these have proved adequate to support a broad range of device types. It was felt that if USB was allowed to increase in complexity, a lack of focus would prevent it from remaining low-cost and achieving widespread usage. As such, the standard was created with the intent that the feature set and cost were in line with the ability of computer manufacturers to provide USB in every platform, and as part of every base configuration – and this intent has been proven in the marketplace.<br />
<br />
This simple design allowed USB to address its targeted applications (which initially were peripherals attached to PC-class computers), and also allowed the vast majority of other device types to find a way to make USB work. Indeed, the different usages of USB have been ever-increasing over the years. Thus, while initially created to ease the difficulties of connecting new hardware to PC-class computers, USB’s simple design philosophy has led to its adoption throughout the computer, consumer electronics and mobile communications industries, into automobiles and industrial automation applications, and for power applications such as recharging batteries as well as providing primary power to computers and many other kinds of devices.<br />
<br />
&#8226;<b><u><i>USB’s Universality</i></u></b><br><br />
There is no other computerized interface in the world that has had anything approaching USB’s widespread acceptance – it is truly ubiquitous, and it has seen a continual increase in usage in an ever-broadening range of product categories since its 1996 introduction. In 2006 alone, over 2 billion USB devices were shipped.<br />
<br />
&#8226;<b><u><i>USB Implementers Forum (USB-IF)</i></u></b><br><br />
Much of USB’s success is due to its having been designed by a broad industry coalition. As key players in that coalition were writing the USB 1.0 Specification, they created the USB Implementers Forum (USB-IF) in 1995 as a nonprofit organization, and whose main activities have been the promotion and marketing of USB, the creation and maintenance of USB ancillary standard specifications, and running a compliance program to ensure adherence to these specifications. Devices proven to comply with the USB-IF certified testing protocol can be sold with a USB-certified logo.<br />
<br />
In addition, the USB “trident” logo was created at the time of the USB 1.0 Specification. The inclusion of this logo on cabling and adjacent to connectors has led to it becoming USB’s most universally recognized symbol. The different shapes at the tips of the trident’s three prongs represent the multiple device types able to be supported by USB, and on a single port.<br />
<br />
&#8226;<b><u><i>USB Timeline</i></u></b><br><br />
• <b>May 1994</b>: Intel invited representatives from major industry players to a meeting at the Intel Jones Farm campus to discuss “Serial Bus,” a new serial protocol that Intel proposed to replace the antiquated serial and parallel interfaces that were then standard on PC class computers. This bus was eventually given the name Universal Serial Bus, or USB.<br><br />
• <b>Sept. 1995</b>: USB was introduced to an industry gathering of about 700 at the Fairmont Hotel in San Jose, CA. When Jim Pappas was introduced, he walked from the back of the room to the stage while dragging behind him a large swath of cables with mice, keyboards and other peripherals attached. He started his keynote address by saying that “all of this can be replaced by just one of these” while holding up a single USB Type A connector. By the time of this event, 160 companies had registered for USB Vendor IDs.<br><br />
• <b>Jan. 15, 1996</b>: Revision 1.0 of the USB Specification as created by seven key industry players (Compaq, Digital Equipment Corporation (DEC), the IBM PC Co., Intel, Microsoft, NEC and Northern Telecom (Nortel)) was made public. It supported speeds of 1.5 Mbits/sec and 12 Mbits/sec.<br><br />
• <b>August 27, 1997</b>: Windows 95 OEM Service Release (OSR) 2.1 was released with support for USB, and over 1100 companies had registered for USB Vendor IDs around this timeframe.<br><br />
• <b>June 25, 1998</b>: Windows 98 was released with support for a draft version of the USB 1.1 spec.<br><br />
• <b>August 15, 1998</b>: the Apple iMac G3 was released without an integrated floppy drive, but with USB 1.1 support for a pair of USB connectors able to support devices including a keyboard and mouse, and with industry support for a floppy drive.<br><br />
• <b>Sept. 23, 1998</b>: Revision 1.1 of the USB Specification was released with various embellishments and clarifications.<br><br />
• <b>April 27, 2000</b>: Revision 2.0 of the USB Specification was released, which added high-speed mode @ 480 Mbits/sec (a 40x improvement).<br><br />
• <b>Nov. 12, 2008</b>: Revision 3.0 of the USB Specification was released, which added SuperSpeed mode @ 5 Gbits/sec (an over 10x improvement).<br><br />
• <b>July 26, 2013</b>: Revision 3.1 of the USB Specification was released, which added SuperSpeedPlus @ 10 Gbits/sec (a 2x improvement), and support for up to 100 Watts of power.<br><br />
• <b>Sept. 22, 2017</b>: Revision USB 3.2 of the USB Specification was released, which added a 2nd data lane for a 2x improvement, and the Type C connector.<br><br />
• <b>August 29, 2019</b>: the USB4 Specification was released, which expanded data transfer modes, including tunneling.<br><br />
|supporting materials=*USB 1.0: https://fl.hw.cz/docs/usb/usb10doc.pdf<br />
*USB 1.1: http://esd.cs.ucr.edu/webres/usb11.pdf / http://www.13thmonkey.org/documentation/USB/usb11.pdf<br />
*USB 2.0: https://www.usb.org/document-library/usb-20-specification<br />
*https://www.intel.com/content/www/us/en/standards/usb-two-decades-of-plug-and-play-article.html<br />
|submitted=No<br />
}}</div>Administrator1http://ieeemilestones.ethw.org/index.php?title=Milestone-Proposal:Universal_Serial_Bus_(USB)&diff=10240Milestone-Proposal:Universal Serial Bus (USB)2021-02-26T15:42:46Z<p>Administrator1: </p>
<hr />
<div>{{Proposal<br />
|docketid=2020-07<br />
|litigation=No<br />
|more than 25 years=Yes<br />
|within fields of interest=Yes<br />
|benefit to humanity=Yes<br />
|regional importance=Yes<br />
|ou is paying=Yes<br />
|ou is arranging dedication=Yes<br />
|section is taking responsibility for plaque=Yes<br />
|a11=Yes<br />
|a3=1996<br />
|a1=Universal Serial Bus (USB), 1996<br />
|plaque citation=An industry consortium published the first Universal Serial Bus (USB) specification in January 1996. Intended to simplify attaching electronic devices to a computer, and initially directed to PCs, USB became a very successful industry-wide interface. Its versatile architecture supported new classes of devices, power delivery, battery charging, and high speed, while remaining low cost for home and business use. USB's cabling, connectors, and logo became recognizable worldwide.<br />
|a2b=Oregon<br />
|IEEE units paying={{IEEE Organizational Unit Paying<br />
|Unit=Oregon Section<br />
|Senior officer name=Paulo Vasconcelos<br />
|Senior officer email=paulo.vasconcelos@ieee.org<br />
}}<br />
|IEEE units arranging={{IEEE Organizational Unit Arranging<br />
|Unit=Oregon<br />
|Senior officer name=Paulo Vasconcelos<br />
|Senior officer email=paulo.vasconcelos@ieee.org<br />
}}<br />
|IEEE sections monitoring={{IEEE Section Monitoring<br />
|Section=Oregon<br />
|Section chair name=Paulo Vasconcelos<br />
|Section chair email=paulo.vasconcelos@ieee.org<br />
}}<br />
|Milestone proposers={{Milestone proposer<br />
|Proposer name=Brian A. Berg<br />
|Proposer email=b.berg@ieee.org<br />
}}<br />
|a2a=Intel Corporation, 2111 NE 25th Ave, Hillsboro, OR 97124 (Intel Jones Farm Campus) 45.543941 122.962248<br />
|a7=In the lobby of the Jones Farm Conference Center (JFCC) on the Intel Jones Farm Campus<br />
|a8=Yes<br />
|mounting details=On a wall in the lobby of the JFCC<br />
|a9=There is a security guard, and the lobby is open to the public during normal business hours<br />
|a10=Intel Corporation<br />
|a4=The key initial importance of USB was its impact on transforming the task of attaching and removing devices from computers from a process that required technical skills and patience into one that was as easy as inserting or removing a cable – a process dubbed as “Plug and Play.” USB thereby made computers more user friendly, whether it be at home, in an office setting, or in a data center. USB’s popularity led to other uses such charging batteries in cell phones and becoming the power connector for computers. As a result, USB has become ubiquitous on most computerized devices, and its logo and cabling are recognized worldwide.<br />
<br />
&#8226;<b><u><i>Expanding the capabilities PC-class computers was difficult before the mid-1990s</i></u></b><br><br />
Until the mid-1990s, it was difficult for anyone without some technical skills to significantly expand the capabilities of IBM PC-class computers. For the general consumer world, such a task was practical only for “hobbyists.” For the business world, an IT department whose staff could configure and support system reconfigurations or expansions was generally required.<br />
<br />
The means by which new hardware could be added to PCs was usually by using one or more of the following: the serial port, the parallel port (which sometimes adhered to the IEEE 488 standard), and an expansion board that was installed in an open slot in the computer’s internal motherboard. For example, adding a new device such as a digital scanner typically required opening up the PC and installing an expansion board that used either SCSI or some proprietary protocol. Such a task could include unscrewing and uncabling some existing components, manipulating jumpers and/or dip switches to configure DMA channels and IRQ request lines, and often much trial and error while having to power the PC on and off each time a change was made before the scanner could operate.<br />
<br />
Many of the problems encountered were due to the lack of standard practices amongst the many suppliers in the industry, and thus the difficulty of describing the necessary steps for adding the new hardware because of, for example, the configuration of devices already installed on the PC. As such, adding new hardware and returning the PC to a fully working condition was often a difficult task even for skilled hobbyists and professionals. The non-technical consumer public would either rely on staff at a computer store to undertake such a task, or they would not even consider adding a new device such as a scanner Retail computer superstore CompUSA reported that their product return rate for scanners was over 30%, and that the impact of these returns resulted in a net loss for the entirety of their scanner sales at that time.<br />
<br />
&#8226;<b><u><i>The Plug and Play Standard</i></u></b><br><br />
An effort called “Plug and Play” (abbreviated as PnP) began in the 1990s as part of an industry-wide effort to allow a PC to automatically self-configure both its hardware and software in order to accommodate the addition of a new device with little or no effort by the user. PnP was intended to be automatically invoked when new hardware was installed inside the PC, but also to accommodate “hot swapping” a device so as to not require the PC to first be powered off. Thus, the computer would automatically recognize any new device, load new software drivers if needed, and allow the newly-connected device to be usable.<br />
<br />
PnP was a collection of methods for determining and controlling system resource usage, and thereby required that a PC’s motherboard, system BIOS and peripherals all be PnP-compliant. A number of hardware and software companies developed the PnP standard for the control of all system resources so that changes could be dynamically performed when the computer was booted after a reconfiguration, as well as by plugging or unplugging a device while the computer was running.<br />
<br />
ISA PnP in 1993 defined hardware methods for detecting and configuring expansion cards, but typically didn’t expect those card to be re-configured during normal operation. A document titled “Plug and Play BIOS Specification Version 1.0A” was published on May 5, 1994 jointly by Compaq Computer Corp., Phoenix Technologies, Ltd. and Intel Corp. to define requirements for the system BIOS aspect of PnP, and soon thereafter Intel started shipping motherboards equipped with a PnP BIOS.<br />
<br />
Released in August 1995, Microsoft’s Windows 95 operating system’s major architectural changes as compared with its Windows 3.1 predecessor were critical to advancing PnP in the industry. Its System Registry worked with a comprehensive scheme of enumerating hardware at boot time, and the ability to dynamically allocate and deallocate resources as hardware was added or removed from a running PC. An essential Windows 95 PnP component was its "Add New Hardware" wizard which recognized when new hardware was attached, and which would guide the user through any steps necessary to allow its use.<br />
<br />
&#8226;<b><u><i>Intel initiated the efforts that led to USB’s creation</i></u></b><br><br />
Intel recognized that PnP needed a whole new interface protocol that would replace the PC’s parallel and serial interfaces with one that supported hot swapping. After initial work on a spec (initially called the “Serial Bus”) had been completed in early 1994, Jim Pappas (who had been working at Digital Equipment Corp., aka DEC) joined Intel and led the effort for this new bus. Intel invited key industry players to join a working group to further develop the spec, and their first meeting was held in May 1994 at Intel’s Jones Farm Campus in Hillsboro, OR. <br />
<br />
The attendees brainstormed about which direction to take and which technical skills to recruit for the effort. This meeting was the birth of what was eventually called the Universal Serial Bus, or USB. This effort resulted in seven companies working together to create USB Specification Revision 1.0 as released on Jan. 15, 1996: Compaq, Digital Equipment Corp. (DEC), the IBM PC Co., Intel, Microsoft, NEC and Northern Telecom (Nortel). USB embraced PnP's self identification and configuration technologies, and required that all USB devices had to be configured before they could be used.<br />
<br />
The introductory chapter of this first USB Specification states that the “motivation for the Universal Serial Bus comes from three interrelated considerations” which it describes as “Connection of the PC to the telephone” (due to “the merge of computing and communication” being “the basis for the next generation of productivity applications”), “Ease of use” (the difficulties resultant from the multiplicity of different means by which a device can be attached to a computer, including the serial/parallel ports discussed above, keyboard/mouse/joystick interfaces, and new interfaces created to accommodate new device types), and “Port expansion” (the limited number of ports in computers). Thus, the “lack of a bi-directional, low-cost, low-to-mid speed peripheral bus has held back the creative proliferation of peripherals.”<br />
<br />
&#8226;<b><u><i>The Importance of Intel’s Jones Farm Campus</i></u></b><br><br />
While the first USB specification was being created, most interactions with outside vendors took place during regularly-scheduled conference calls. Outside vendors such as Microsoft often came to meetings at Jones Farm, and face-to-face meetings were generally hosted by various companies elsewhere. However, the Jones Farm Campus became the "epicenter" of this endeavor as hardware and software was being developed and tested collaboratively.<br />
<br />
There is a glass conference room at the entrance of the Jones Farm 3 building (JF3) that was unique since it was accessible prior to reaching the security desk, and it had been a private conference room reserved for the most senior Intel executives. This room was allowed to be converted into a lab for a 3-month period, but it ended up being used for over 3 years by nearly every company working in the ever-growing USB industry. Dubbed the USB Product Integration Lab (PIL), it could be occupied by various companies 24 hours a day, even after the lobby was closed. As there were no USB devices, hubs or hosts in the early days, Intel created debug versions of these devices along with software drivers and test tools. All of the original furniture in the PIL was replaced with several lab benches, and every bench was filled with these debugging tools along with test equipment. Companies developing new USB products were able to use the PIL as a test and debug environment while working with Intel USB engineers in order to get USB signaling, packets and transactions operational. The companies using the PIL were often very secretive about the products that they had under development. Until at least 1996, most industry players involved in early development efforts used the PIL to debug their USB products before they went into production. Key to this effort was the availability of the first USB ICs from Intel in 1995.<br />
<br />
&#8226;<b><u><i>USB played an essential role in transitioning the PC into a consumer-level device</i></u></b><br><br />
The USB standard was created by the industry to allow the PC to expand beyond just business applications by enabling a consumer-friendly way to add devices to a computer, and also enabling new usage areas such as digital music and digital photography. Essential to USB was a standard connector on the exterior of the computer which allowed any type of USB device to be dynamically plugged into or unplugged from a running computer. Most computers included at least two such connectors, and a USB hub allowed multiple devices to be supported from a single USB connector.<br />
<br />
The fact that PnP was an essential aspect of the new Windows 95 architecture allowed the addition of support for USB by way of OEM Service Release (OSR) 2.1, which became available on August 27, 1997. Nearly every industry player, including Microsoft itself, used the USB PIL to debug and validate their products since Windows 95 was the first operating system to support the new USB standard.<br />
<br />
USB reached a critical turning point with the June 1998 release of Windows 98 because of its support of a draft version of the USB 1.1 spec. With Windows being the world’s most popular operating system, the number of USB devices on the market began to grow dramatically. In addtion, Apple's iMac (announced in May 1998 and released in August 1998) replaced its normal mouse and keyboard connectors with a pair of USB connectors.<br />
|a6=&#8226;<b><u><i>Technical Obstacles</i></u></b><br><br />
USB’s most significant technical challenge was containing costs. The USB design target included the mouse, the single most common pointing device at the time. Microsoft disclosed that the entire electronics budget for their optical mouse was only 50 cents. Using the mouse as the baseline, this design target set up a series of challenges regarding how to keep the design simple and inexpensive, while still allowing it to expand into areas such as imaging, storage, and synchronous applications such as music and digital telephony.<br />
<br />
A second significant technical obstacle arose due to the desire to minimize cost. The challenge was how to accomplish all the desired communication and control functionalities using only a single differential signaling pair - essentially one logical wire. In comparison, other popular cabled connections of the time used many wires, with wires dedicated to special signals such as interrupts.<br />
<br />
&#8226;<b><u><i>Broad Acceptance Obstacle</i></u></b><br><br />
USB faced a critical obstacle for its acceptance and success in the marketplace. The industry recognized the need for a simplified low-cost interface that used a single connector to support a variety of hot-swappable devices, and USB’s main competition in achieving this was IEEE 1394/FireWire and ACCESS.bus:<br><br />
• <u>IEEE 1394/FireWire:</u><br><br />
&nbsp;&nbsp;o Like USB, it included both power and data on its cabling, but 1394 provided more power<br><br />
&nbsp;&nbsp;o Like USB, it supported hot-swapping (and hence could potentially be plug-and-play)<br><br />
&nbsp;&nbsp;o USB had significantly lower cost than 1394 because of its simplicity (use of a host master) as compared with 1394’s symmetric and more complex peer-to-peer architecture, as well as because its initial design was as a lower-performance interface than 1394<br><br />
&nbsp;&nbsp;o While Steve Jobs was receiving a royalty from PC OEMs of $1 for each 1394 port, Intel was adding USB to its own processor chipset. Since the resultant PC OEM cost of adding USB was thus little more than the cost of adding a pair of USB connectors, the incentive to include 1394 ports in PCs was greatly diminished.<br><br />
&nbsp;&nbsp;o As a result, USB connectors were included on most new PCs near the time of USB’s 1996 introduction, and USB was supported in Microsoft Windows in 1997<br><br />
&nbsp;&nbsp;o USB thus marginalized 1394 to a higher-priced echelon of the consumer electronics market<br><br />
• <u>Apple Desktop Bus (ADB):</u><br><br />
&nbsp;&nbsp;o Proprietary to Apple, and so never a direct USB competitor<br><br />
&nbsp;&nbsp;o Only ever used for low-speed devices such as keyboards and mice<br><br />
&nbsp;&nbsp;o Did not support hot swapping<br><br />
&nbsp;&nbsp;o Introduced on the Apple IIGS in 1986, and used on Apple products until the early 2000s<br><br />
&nbsp;&nbsp;o Used on some NeXT computers, and some third-party computers<br><br />
&nbsp;&nbsp;o Apple replaced ADB with USB starting with the 1998 iMac (which also included FireWire)<br><br />
• <u>ACCESS.bus (A.b)</u><br><br />
&nbsp;&nbsp;o Created by Philips and DEC for the PC as a way to reproduce much of what ADB offered<br><br />
&nbsp;&nbsp;o Supported hot swapping, but its 10 kbit/sec and 100 kbit/sec speeds were much slower than USB’s slowest speeds of 1.5 Mbits/sec and 12 Mbits/sec<br><br />
&nbsp;&nbsp;o ACCESS.bus Industry Group (ABIG) was formed in 1993, and included Microsoft and DEC<br><br />
&nbsp;&nbsp;o Interest waned with Intel’s backing of USB, leaving Philips as the prime supporter<br><br />
&nbsp;&nbsp;o ACCESS.bus thus never achieved widespread use<br><br />
<br />
&#8226;<b><u><i>Political Obstacle</i></u></b><br><br />
A “political” obstacle occurred once it was obvious that USB had broad industry support. A wide variety of requests started to arrive from adjacent markets that wanted to utilize the ubiquity and low cost expected from USB, including numerous requests for additional features which would have expanded the design of USB well beyond its original simple objectives. Examples include (1) fully symmetric and autonomous operation so that devices could communicate even if the PC was powered off, (2) long range cable lengths of up to 1 km, and (3) waterproof connectors for underwater dive computers.<br />
|a5=&#8226;<b><u><i>USB’s Asymmetric Design Allowed for Simplicity and Lower Cost</i></u></b><br><br />
USB was based on a strategic design choice of being asymmetric to take advantage of the fact that the host side interface would have the extensive resources available to a full PC, thus allowing design choices for the device side of the wire to be relatively simple. This decision was hugely beneficial as it (1) allowed the capabilities of a USB device to range from ultra-simplistic to highly sophisticated, (2) differentiated USB from the symmetric design and resultant higher cost of IEEE 1394/FireWire, and (3) led to a broad range of types of USB devices being possible, and which was ever-expanding.<br />
<br />
&#8226;<b><u><i>USB’s Inclusion of Power in Its Cabling</i></u></b><br><br />
The early decision to supply power to attached devices was quite controversial as no widely-used computer interface provided power at that time. The main reason for this was to accommodate devices such as keyboards and mice, which could not have a separate power supply connection. Other devices were also envisioned that could be fully powered from the bus.<br />
<br />
A big surprise was when Logitech completely re-engineered its prototype portable sheet scanner (including the use of new motors) to operate within USB’s 2.5 Watt limit. The inclusion of power often precluded the need for a wall plug power adapter (often called a “wall wart”), and this also had a huge positive impact since it allowed a single cable to attach a wide variety of devices to a PC.<br />
<br />
&#8226;<b><u><i>USB’s Inclusion of Power Allowed it to Eventually Function as a Charger</i></u></b><br><br />
USB’s inclusion of power proved to be hugely beneficial to USB’s success in ways that were far beyond what anyone had envisioned in the mid-1990s. Starting in around 2006, a number of cell phone suppliers (most notably Motorola and Nokia) developed an ancillary specification for the Micro-USB connector specification that would better serve the mobile phone market. In around 2007, Qualcomm and Nokia led an effort to develop the Battery Charging Specification to enable increasing the 5-volt supply current beyond 500 mA when used for mobile phone charging. Thus, USB ports could offer up to 1.5A (7.5 Watts) when enabled for charging using a standardized discovery technique based on the termination of the USB 2.0 data bus pins, and this scheme served the mobile phone industry for several years.<br />
<br />
Starting in 2012, competitive pressures in the explosively expanding cell phone market led to interoperability issues with the standard USB Micro-B connector as proprietary charging techniques that pushed the power boundaries beyond the USB standard's 5V @ 1.5A limitation came into use. One example is Qualcomm’s Quick Charge (QC) technology.<br />
<br />
With the formal introduction of the USB Type-C connector in 2014, and based on the methodologies of the 2012 USB Power Delivery standard, a fully standardized USB charging solution tailored to a broad range of applications became available, and these standards have matured with the marketplace. The USB 3.1 standard allowed USB to deliver up to 100 Watts of power, and USB 3.2 standard included the previously standardized Type-C connector.<br />
<br />
&#8226;<b><u><i>USB’s Simple Design Was Essential to Its Success</i></u></b><br><br />
The USB standard purposefully defined several standard device classes including mass storage, audio, video and communication. These device classes allowed OS vendors to provide standardized device drivers, and avoided having every device vendor provide their own driver. This further reduced errors in the field due to incorrectly implemented device drivers, and these have proved adequate to support a broad range of device types. It was felt that if USB was allowed to increase in complexity, a lack of focus would prevent it from remaining low-cost and achieving widespread usage. As such, the standard was created with the intent that the feature set and cost were in line with the ability of computer manufacturers to provide USB in every platform, and as part of every base configuration – and this intent has been proven in the marketplace.<br />
<br />
This simple design allowed USB to address its targeted applications (which initially were peripherals attached to PC-class computers), and also allowed the vast majority of other device types to find a way to make USB work. Indeed, the different usages of USB have been ever-increasing over the years. Thus, while initially created to ease the difficulties of connecting new hardware to PC-class computers, USB’s simple design philosophy has led to its adoption throughout the computer, consumer electronics and mobile communications industries, into automobiles and industrial automation applications, and for power applications such as recharging batteries as well as providing primary power to computers and many other kinds of devices.<br />
<br />
&#8226;<b><u><i>USB’s Universality</i></u></b><br><br />
There is no other computerized interface in the world that has had anything approaching USB’s widespread acceptance – it is truly ubiquitous, and it has seen a continual increase in usage in an ever-broadening range of product categories since its 1996 introduction. In 2006 alone, over 2 billion USB devices were shipped.<br />
<br />
&#8226;<b><u><i>USB Implementers Forum (USB-IF)</i></u></b><br><br />
Much of USB’s success is due to its having been designed by a broad industry coalition. As key players in that coalition were writing the USB 1.0 Specification, they created the USB Implementers Forum (USB-IF) in 1995 as a nonprofit organization, and whose main activities have been the promotion and marketing of USB, the creation and maintenance of USB ancillary standard specifications, and running a compliance program to ensure adherence to these specifications. Devices proven to comply with the USB-IF certified testing protocol can be sold with a USB-certified logo.<br />
<br />
In addition, the USB “trident” logo was created at the time of the USB 1.0 Specification. The inclusion of this logo on cabling and adjacent to connectors has led to it becoming USB’s most universally recognized symbol. The different shapes at the tips of the trident’s three prongs represent the multiple device types able to be supported by USB, and on a single port.<br />
<br />
&#8226;<b><u><i>USB Timeline</i></u></b><br><br />
• <b>May 1994</b>: Intel invited representatives from major industry players to a meeting at the Intel Jones Farm campus to discuss “Serial Bus,” a new serial protocol that Intel proposed to replace the antiquated serial and parallel interfaces that were then standard on PC class computers. This bus was eventually given the name Universal Serial Bus, or USB.<br><br />
• <b>Sept. 1995</b>: USB was introduced to an industry gathering of about 700 at the Fairmont Hotel in San Jose, CA. When Jim Pappas was introduced, he walked from the back of the room to the stage while dragging behind him a large swath of cables with mice, keyboards and other peripherals attached. He started his keynote address by saying that “all of this can be replaced by just one of these” while holding up a single USB Type A connector. By the time of this event, 160 companies had registered for USB Vendor IDs.<br><br />
• <b>Jan. 15, 1996</b>: Revision 1.0 of the USB Specification as created by seven key industry players (Compaq, Digital Equipment Corporation (DEC), the IBM PC Co., Intel, Microsoft, NEC and Northern Telecom (Nortel)) was made public. It supported speeds of 1.5 Mbits/sec and 12 Mbits/sec.<br><br />
• <b>August 27, 1997</b>: Windows 95 OEM Service Release (OSR) 2.1 was released with support for USB, and over 1100 companies had registered for USB Vendor IDs around this timeframe.<br><br />
• <b>June 25, 1998</b>: Windows 98 was released with support for a draft version of the USB 1.1 spec.<br><br />
• <b>August 15, 1998</b>: the Apple iMac G3 was released without an integrated floppy drive, but with USB 1.1 support for a pair of USB connectors able to support devices including a keyboard and mouse, and with industry support for a floppy drive.<br><br />
• <b>Sept. 23, 1998</b>: Revision 1.1 of the USB Specification was released with various embellishments and clarifications.<br><br />
• <b>April 27, 2000</b>: Revision 2.0 of the USB Specification was released, which added high-speed mode @ 480 Mbits/sec (a 40x improvement).<br><br />
• <b>Nov. 12, 2008</b>: Revision 3.0 of the USB Specification was released, which added SuperSpeed mode @ 5 Gbits/sec (an over 10x improvement).<br><br />
• <b>July 26, 2013</b>: Revision 3.1 of the USB Specification was released, which added SuperSpeedPlus @ 10 Gbits/sec (a 2x improvement), and support for up to 100 Watts of power.<br><br />
• <b>Sept. 22, 2017</b>: Revision USB 3.2 of the USB Specification was released, which added a 2nd data lane for a 2x improvement, and the Type C connector.<br><br />
• <b>August 29, 2019</b>: the USB4 Specification was released, which expanded data transfer modes, including tunneling.<br><br />
|supporting materials=*[[media:Usb-two-decades-of-plug-and-play-article.pdf]]<br />
*[[media:USB-2.0.pdf]]<br />
*[[media:USB-1.1.pdf]]<br />
*[[media:USB-1.0.pdf]]<br />
*[[media:PnP-BIOS-Specification-V1.0A.pdf]]<br />
|submitted=No<br />
}}</div>Administrator1http://ieeemilestones.ethw.org/index.php?title=File:Usb-two-decades-of-plug-and-play-article.pdf&diff=10239File:Usb-two-decades-of-plug-and-play-article.pdf2021-02-26T15:41:01Z<p>Administrator1: </p>
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<div></div>Administrator1http://ieeemilestones.ethw.org/index.php?title=File:USB-2.0.pdf&diff=10238File:USB-2.0.pdf2021-02-26T15:40:52Z<p>Administrator1: </p>
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<div></div>Administrator1http://ieeemilestones.ethw.org/index.php?title=File:USB-1.1.pdf&diff=10237File:USB-1.1.pdf2021-02-26T15:40:42Z<p>Administrator1: </p>
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<div></div>Administrator1http://ieeemilestones.ethw.org/index.php?title=File:USB-1.0.pdf&diff=10236File:USB-1.0.pdf2021-02-26T15:40:34Z<p>Administrator1: </p>
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<div></div>Administrator1http://ieeemilestones.ethw.org/index.php?title=File:PnP-BIOS-Specification-V1.0A.pdf&diff=10235File:PnP-BIOS-Specification-V1.0A.pdf2021-02-26T15:40:27Z<p>Administrator1: </p>
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<div></div>Administrator1http://ieeemilestones.ethw.org/index.php?title=Milestone-Proposal:Commercialization_of_the_fishfinder,_1948&diff=9877Milestone-Proposal:Commercialization of the fishfinder, 19482021-01-21T14:28:57Z<p>Administrator1: Redirected page to Milestone-Proposal:FURUNO</p>
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<div>#REDIRECT [[Milestone-Proposal:FURUNO]]</div>Administrator1http://ieeemilestones.ethw.org/index.php?title=Milestone-Proposal:The_Manchester_University_%27Baby%27_computer;_Small-Scale_Experimental_Machine_(SSEM)&diff=9863Milestone-Proposal:The Manchester University 'Baby' computer; Small-Scale Experimental Machine (SSEM)2021-01-19T13:59:06Z<p>Administrator1: Administrator1 moved page Milestone-Proposal:The Ferranti 'Baby'; Small-Scale Experimental Machine (SSEM) to Milestone-Proposal:The Manchester University 'Baby' computer; Small-Scale Experimental Machine (SSEM)</p>
<hr />
<div>{{Proposal<br />
|docketid=2020-09<br />
|litigation=No<br />
|more than 25 years=Yes<br />
|within fields of interest=Yes<br />
|benefit to humanity=Yes<br />
|regional importance=Yes<br />
|ou is paying=Yes<br />
|ou is arranging dedication=Yes<br />
|section is taking responsibility for plaque=Yes<br />
|a11=Yes<br />
|a3=1948 - 1951<br />
|a1=The world’s first electronic stored program digital computer, 1948.<br />
|plaque citation=At this site on 21 June 1948 the world’s first electronic stored program digital computer successfully ran a program. Designed and built at the University of Manchester by F.C. Williams and T. Kilburn, it incorporated a successful random-access memory and subsequently contained the first index registers. Based on this design, the world's first commercially produced computer, the Ferranti Mark I, was delivered to the University on 12 February 1951.<br />
|a2b=UK & Ireland Section, Region 8<br />
|IEEE units paying={{IEEE Organizational Unit Paying<br />
|Unit=UK & Ireland Section, Region 8<br />
|Senior officer name=Professor Rod Muttram FREng, SMIEEE<br />
|Senior officer email=rod.muttram@ieee.org<br />
}}<br />
|IEEE units arranging={{IEEE Organizational Unit Arranging<br />
|Unit=UK & Ireland Section, Region 8<br />
|Senior officer name=Professor Rod Muttram FREng, SMIEEE<br />
|Senior officer email=rod.muttram@ieee.org<br />
}}<br />
|IEEE sections monitoring={{IEEE Section Monitoring<br />
|Section=UK & Ireland Section, Region 8<br />
|Section chair name=Mona Ghassemian<br />
|Section chair email=mona.ghassemian@ieeer8.org<br />
}}<br />
|Milestone proposers={{Milestone proposer<br />
|Proposer name=Professor Roderick I Muttram CEng, FREng, FIET, FIRSE, SMIEEE<br />
|Proposer email=rod.muttram@ieee.org<br />
}}{{Milestone proposer<br />
|Proposer name=Roland Ibbett FRSE, FBCS, CEng, SMIEEE<br />
|Proposer email=Roland.Ibbett@bcs.org.uk<br />
}}{{Milestone proposer<br />
|Proposer name=Professor Simon Lavington, CEng, FIET, FBCS,<br />
|Proposer email=lavis@essex.ac.uk<br />
}}{{Milestone proposer<br />
|Proposer name=James Miles<br />
|Proposer email=jim.miles@manchester.ac.uk<br />
}}<br />
|a2a=Bridgeford Street, Manchester M13 9PL. 53 .466218 -2.<br />
|a7=The plaque will be mounted on the outside of the Coupland 1 Building, Bridgeford Street, in a place where the plaque will be viewable by the public.<br />
|a8=Yes. The implementation of the computer and its historic first demonstration took place in the Coupland I Building., where the plaque will be located.<br />
|mounting details=The University of Manchester’s provisional plan for the precise location is that the IEEE plaque would replace the existing informational plaque shown in Fig. 1 of the accompanying collection of images<br />
|a9=The public will be able to view the plaque at all hours. Bridgeford Street is pedestrianised and at night this area of the University of Manchester is regularly patrolled by security staff.<br />
|a10=The University of Manchester<br />
|a4=On the morning of 21st June 1948 the Small-Scale Experimental Machine (SSEM), also called the Baby, was the first electronic stored program digital computer to run a program [ref. 1a, 1b]. Fig. 2 in the accompanying collection of images gives an impression of the moment when a factoring program completed its first successful run of about 52 minutes’ duration, having executed some 3.5 million operations. <br />
<br />
Looking back, one could say that the 21st June 1948 marked the start of software development and the birth of the Computer Age. When the SSEM first worked, however, it was noticed by contemporary computing pioneers more for its memory system than for its first program – which was small, only 25 instructions [ref. 1c]. The SSEM’s memory system was important because at that time “The most difficult problem in the construction of large-scale digital computers continues to be the question of how to build a memory” [ref. 2]. <br />
<br />
<b><i>Memory Development</i></b><br />
<br />
In the post-war years several potential memory technologies were being suggested, such as: thermionic valves, electro-mechanical relays, magnetic drums, tape or wire; mercury or magneto-strictive delay lines; charge-storage devices. The important design parameters for a computer’s primary memory included: capacity, access-time, cost per bit, reliability. At Manchester, F C Williams and T Kilburn led the way and successfully patented their memory-related inventions [Ref. 3(a)]. So important was the SSEM’s memory technology that it was soon adopted by other pioneering computer design groups, particularly John von Neumann’s group at Princeton and IBM for the 701 and 702 production computers.<br />
<br />
The SSEM’s memory system, called Williams-Kilburn Tubes, was based on electrostatic charge-storage and was random-access [ref. 3a, 3b, 3c]. See also Fig. 4 in the accompanying collection of images. In Williams-Kilburn Tubes, selection of a digit was achieved by deflecting an electron beam. Since selection-time was independent of physical location, Williams-Kilburn Tubes offered the first practical implementation of RAM (random-access memory). Most other contemporary memory devices under consideration were of the delay-line type, whose access was sequential (not random). The first computer to become operational using mercury delay line storage was the Cambridge University EDSAC, in May 1949.<br />
<br />
The SSEM’s Williams-Kilburn Tubes were the first random-access memory system to have become operational. Other pioneering design teams such as that of John von Neumann at Princeton were hoping to use a random-access memory device called the Selectron [ref. 4], once it had been perfected by RCA. In the event the Selectron was never made available so Princeton adopted Williams-Kilburn Tubes. IBM followed suit, licensing Williams-Kilburn Tubes for their 701 computers. The Whirlwind project at MIT developed a special holding beam storage tube, which was random-access but considerably more complex than Williams-Kilburn tubes. Whirlwind first did useful work in March 1951. The Princeton computer first did useful work in the summer of 1951.<br />
<br />
The cost per bit of Williams-Kilburn Tubes made them an economically attractive technology for central registers as well as for primary memory. One Williams-Kilburn Tube could easily store eight 32-bit central registers, at about one fiftieth the cost-per-bit of flip-flop registers. This fact soon led the SSEM team to add a set of general-purpose index (or modifier) registers to their computer – a significant architectural innovation still in use today [ref. 5(a), 5(b)]. <br />
<br />
<b><i>Further enhancements</i></b><br />
<br />
From July 1948 the University team made the following enhancements to the SSEM: increasing the primary memory; extending the word-length from 32 to 40 bits and adding a double-length accumulator; increasing the instruction repertoire to 26 orders, including fast hardware multiply; adding modifier registers; adding a magnetic drum secondary memory with a unique coding system (Phase Encoding, still in use today) [ref. 13]. With the drum secondary memory becoming operational in June 1949, the Manchester computer was probably the first machine to contain the now-familiar combination of two levels of on-line storage: a fast but smaller primary section plus a slower but larger secondary memory.<br />
<br />
<b><i>Commercialisation</i></b><br />
<br />
The strategic importance of the SSEM and its memory system were quickly recognised. In October 1948 Sir Ben Lockspeiser, Chief Scientist at the Ministry of Supply (MOS), paid the SSEM a visit. On 26th October Lockspeiser initiated a UK government contract with the long-established electrical company Ferranti Ltd. to produce a fully-engineered production version of the SSEM [ref. 6]. The resulting production computer was named the Ferranti Mark I. See Fig. 5 in the accompanying collection of images. <br />
<br />
In total, the company produced two Ferranti Mark I computers and seven upgraded versions, the Mark I* (pronounced Mark One Star). See also Fig. 6 in the accompanying collection of images. A Ferranti Mark I was installed at the University of Manchester on Monday 12th February 1951 – a world first for the delivery of a commercially-available computer. Constructional details of the Ferranti Mark I are described in [ref. 14a]. The background to the academic/industrial co-operations which led to the Ferranti Mark I are given in [ref. 14b]. <br />
<br />
By the mid-1950s American companies such as Univac and IBM were installing tens of general-purpose computers in the USA. For various reasons both economic and strategic, it was not until about 1956 that American-produced computers reached non-American destinations. It seems that, in the period 1951 to 1955, Ferranti Ltd. was the only manufacturer willing and able to deliver more widely [ref. 7]. Thus, the first substantial computers to be delivered and put to use in Canada, Holland, Italy and the UK were Ferranti Mark I or Mark I* machines. The first non-British computer to reach the UK was an IBM 650, delivered in October 1956 [ref. 7].<br />
<br />
Whilst the hardware and architecture of early Manchester and Ferranti computer designs was innovative and patented [ref. 3a], the software was initially far from user-friendly. Steps were soon taken to improve this [ref. 8a]. By 1954 an Autocode had been developed and “the Mark I became possibly the easiest machine to program in Britain” [ref. 8b]. The Mark I Autocode, probably the first high-level language, was released to users in March 1954; this was a year or two ahead of the US Fortran developments.<br />
|a6=The development path which led to the SSEM at Manchester University was not smooth. The storage research was begun by F C Williams in August 1946 in the government’s prestigious Telecommunications Research Establishment (TRE). TRE had several other higher-priority projects in development at the time, such as guided weapons systems. In December 1946 Williams’ storage project transferred to the University of Manchester’s Department of Electro-technics when Williams was appointed Professor. He inherited a Department in the doldrums after staff resignations [ref. 10]. In particular it lacked any existing electronics staff or electronics equipment. So Williams was fortunate to get agreement to import all his research resources from TRE, free of charge to the University. Freddie Williams’ close TRE colleague Tom Kilburn was seconded to Manchester and registered for a Ph.D. The TRE engineer Arthur Marsh was also transferred but quickly decided that ‘there was no future in digital computers’ [ref. 1(c)]. Fortunately TRE seconded a replacement engineer, Geoff Tootill, who was enthusiastic. The SSEM was developed by Williams, Kilburn and Tootill, using TRE resources.<br />
<br />
There is, of course, more to a computer than its memory system and central processor hardware. In 1949 Williams said: “When I first entered the field of computers, fresh from the field of radar after the war, I was prepared to believe you could do a lot with electronics because I had had some experience of it, but the stumbling block, the thing I didn’t see, was how the programme was organised to be put onto these [computing] machines with a finite amount of effort and of space in the machine”. [ref. 11]. Help was needed from the mathematicians.<br />
<br />
Fortunately Manchester’s Mathematics Professor Max Newman, who had supported F C Williams’ appointment, was interested in the possible uses of general-purpose computers. In May 1946 Newman had obtained a Royal Society grant of £35,000 to set up a Computing Machine Laboratory to investigate mathematical applications. Newman and one of his mathematics lecturers, I J Good, had spent a week visiting Alan Turing at the National Physical Laboratory to gain ideas. Then Newman had spent three months in the autumn of 1946 visiting John von Neumann’s computer design group at the Institute for Advanced Study, Princeton. It seems that Max Newman and Jack Good hoped to acquire a computing machine of a similar nature to von Neumann’s using Selectron storage tubes [ref. 12], but this never happened. <br />
<br />
Unfortunately Jack Good left Manchester in April 1948 but the outstanding mathematician Alan Turing joined Newman in October 1948. Turing’s salary was the first call upon the Royal Society grant. Thus, Newman and Turing were fortunately in place in 1949 to advise Williams and Kilburn on system software for the enhanced Manchester computer. See Fig. 3 in the accompanying collection of images. Newman and Turing also specified the first useful program (investigation of Mersenne Primes) in April 1949. Finally, Newman agreed to spend £20,000 of his grant on the provision of a new, custom-designed, Computing Machine Laboratory which was required to house the Ferranti Mark I computer when it was delivered in February 1951.<br />
|a5=Manchester University’s early computer design efforts were characterised by the production of useful results by a small academic team, leading to fruitful co-operation with local industry. From January 1947 to September 1948 the hardware team essentially consisted of just three people: F C Williams, T Kilburn and G C Tootill. In September 1948 they were joined by three hardware research students. <br />
<br />
The hardware designs were passed to Ferranti Ltd. in the period between December 1948 and November 1949, with appropriate exchange of personnel between academia and industry. About 35 patents were filed by F C Williams and colleagues at Manchester University between November 1947 and March 1950 [ref. 3(a)]. This was almost three times the total number of patents filed by all the other UK computer design groups over the same period.<br />
<br />
On the software side, Alan Turing came to Manchester University in October 1948. Alan Turing was responsible for the input/output routines and other basic library subroutines of the early Manchester computers. An assistant mathematician, Cicely Popplewell, was appointed in October 1949. Then in October 1951 R A (Tony) Brooker arrived to head up the University’s Computing Service. In summary, the software team associated with the early Manchester computers was relatively small.<br />
<br />
Alan Turing and Max Newman were the first users of the early Manchester computer. Useful theoretical work was done in the spring of 1949 and in the period October 1949 to August 1950, investigating Mersenne primes and the Riemann hypothesis. A more practical application involved optical ray tracing for high-precision lens design. There was then a pause whilst a new building, the Computing Machine Laboratory, was completed to house the production computer. The Ferranti Mark I arrived in February 1951. Alan Turing issued the 100-page Users’ Programming Manual in March 1951. <br />
<br />
From its very small beginnings in 1948, use of the computing facilities at Manchester University grew rapidly after the installation of the Ferranti Mark I. During calendar year 1955, 104 people were trained to use the machine and 66 scientific papers were published based on machine results [ref. 1c]. The community of users at Manchester had grown to include 15 University departments, three industrial research associations, seven engineering companies and nine government establishments [ref. 1c]. By 1955 a total of seven Ferranti-manufactured derivatives of the SSEM had been installed at customer’s sites and a further two computers would be installed by the end of 1957. The nine sites together covered four countries: UK, Canada, Holland and Italy [ref. 7]. The influence of the 1948 SSEM (the Baby) therefore grew, making a significant presence on the world stage.<br />
|references=. (a). F C Williams & T Kilburn, Electronic digital computers. Letter to Nature, vol. 162, September 1948, page 487. This Letter includes the following text: “A small electronic digital computing machine has been operating successfully for some weeks in the Royal Society Computing Machine Laboratory, which is at present housed in the Electrical Engineering Department of the University of Manchester. The machine is purely experimental, and is on too small a scale to be of mathematical value. It was built primarily to test the soundness of the storage principle employed and to permit experience to be gained with this type of machine before embarking on the design of a full-size machine. However, apart from its small size, the machine is, in principle, 'universal' in the sense that it can be used to solve any problem that can be reduced to a programme of elementary instructions; the programme can be changed without any mechanical or electro-mechanical circuit changes. … It will, of course, be understood that it is intended to have other arithmetical facilities, as well as a much larger store, in a full-sized machine … At present routines are chosen with the sole object of testing the machine as thoroughly as possible. The development of this machine has been very actively supported by the Telecommunications Research Establishment, Great Malvern”. See also Fig. 2 in the accompanying collection of images.<br />
<br />
1 (b). M H A Newman, Status Report on the Royal Society Computing Machine Laboratory, prepared for an internal committee of the Senate of the University of Manchester, 15th October 1948. Max Newman, Professor and Head of Mathematics at Manchester University, had obtained a grant from the Royal Society in May 1946 to establish a Computing Machine Laboratory. In his October 1948 Report Newman explains the difficulties in acquiring a digital computing machine for his proposed Laboratory. He highlights the engineering problems in finding “a satisfactory memory unit or method of storage of information” and the delays in obtaining Selectron memory units from RCA. Newman goes on to state that “a small prototype of the [digital computing] machine using Professor Williams’ storage came into action about three months ago in the Electrical Engineering Laboratory and is thus the first of these automatic general-purpose computing machines to have actually worked”. The mathematician Max Newman had led the Colossus cryptanalytical group at Bletchley Park during the war. Newman kept in touch with John von Neumann at the Institute of Advanced Study at Princeton and had visited their computer design group at Princeton from October to December 1946. Newman had organised a Discussion on Computing Machines at the Royal Society, London, on 4th March 1948 at which there were short presentations from most of the UK’s embryo computer design projects. Max Newman would therefore have been aware of any stored-program machine that might have pre-dated the SSEM. It is believed that the main challenger was the EDSAC computer at the University of Cambridge, which first ran a program on 6th May 1949. <br />
<br />
1 (c). The first program is reproduced in: S H Lavington, A History of Manchester Computers, Second edition, published in 1998 by the British Computer Society. ISBN 0-902505-01-8.<br />
<br />
2. Nathaniel Rochester (IBM), Radio progress during 1949: electronic computers. Keynote paper in the Proceedings of the IRE, April 1950, page 374. <br />
<br />
3 (a). The Williams Tube (or more strictly the Williams-Kilburn Tube) stored digital information as a matrix of electrostatically-charged areas on the phosphor coating of a cathode ray tube. See Fig. 4 in the accompanying collection of images. The unique feature of the Williams Tube was its method of automatically refreshing the charge pattern before it decayed. The economic benefit of the system was its low cost per bit: it could be built from standard CRTs. The first patent for Williams Tube memory was UK Application Number GB19460036587, with the title of Apparatus for storing trains of pulses. This was filed on 11th December 1946 in the name of F C Williams who was at the time employed by the government’s Telecommunications Research Establishment. A number of subsequent storage patents followed, mostly in the joint names of F C Williams and T Kilburn. The list of all patents emanating from F C Williams’ Manchester University computer design team in the period January 1947 to 1st March 1950 is given below, based on an analysis of all patents from January 1943 to October 1991 inherited by or administered by NRDC. (This analysis was compiled in 2018 by Roger Cullis, a former NRDC senior patent attorney, using data from the European Patent Office World Patents Index). The time-period of the following Manchester University patents embraces all the novel technical developments associated with the SSEM and its subsequent enhancements. <br />
Date Title of patent Name(s) of inventors<br />
20/10/47 Electrical information storage apparatus FCW, TK<br />
22/05/48 Information storage means FCW, TK<br />
26/07/48 Improvements in or relating to electronic ccts for digital comp. systems FCW, TK<br />
26/07/48 Electronic circuit for adding binary numbers FCW, TK<br />
13/10/48 Electronic digital computing apparatus FCW, TK<br />
01/11/48 Electrical information storage apparatus FCW, TK<br />
23/12/48 Pulse selecting circuits FCW, AAR, TK<br />
23/12/48 Circuit for adding binary numbers FCW, AAR, TK<br />
23/12/48 Circuit for multiplying binary numbers AAR<br />
23/12/48 Pulse selecting circuits FCW, AAR, TK<br />
31/01/49 Electronic digital computing device FCW, TK<br />
1/03/49 Magnetic storage systems for electronic binary digital computers FCW, JCW<br />
1/03/49 Magnetic storage systems FCW<br />
14/03/49 Improvements in or relating to electronic ccts for multiplying binary nos FCW, AAR<br />
14/03/49 Electronic circuit for multiplying binary numbers FCW, AAR<br />
3/06/49 Electronic digital computing devices [This patent refers to B-lines, later known as Index registers] FCW, TK, GCT, AAR, MHAN<br />
7/06/49 Electrical information storage means FCW, TK, GCT<br />
7/06/49 Improvements in or relating to electronic digital computors FCW, TK, GCT<br />
7/06/49 Electronic digital computers FCW, TK<br />
22/06/49 Electronic digital computing machines FCW, AAR<br />
22/06/49 Electronic digital computing machines FCW, TK, GCT, GET,<br />
DBGE<br />
22/06/49 Electronic computing devices with subsidiary storage FCW, TK, GET, DBGE, GCT<br />
22/06/49 Improvements in or relating to digital computors FCW, TK, GET, DBGE, GCT<br />
22/06/49 Improvements in or relating to electronic digital computing machines FCW, TK, GET, DBGE, GCT<br />
22/06/49 Electronic digital computing machines AAR, FCW, TK <br />
8/08/49 Electrical signal detecting and amplifying systems FCW, TK<br />
17/08/49 Electronic digital computing machines FCW, TK<br />
17/08/49 Electronic digital computing machines FCW, TK, GCT<br />
14/11/49 Electronic storage devices FCW, TK<br />
14/11/49 Electronic information storage devices FCW, TK, GCT<br />
16/11/49 Digital computing machine FCW, TK, GET<br />
16/11/49 Improv in magnetic rec or reproducing devices partic for dig comp mcs FCW, TK, GET<br />
22/11/49 Electronic information-storing devices FCW, TK<br />
1/12/49 Electrical storage apparatus FCW, TK, GCT<br />
19/01/50 Electronic information storage device FCW<br />
16/02/50 Improvements in or relating to electronic information-storing devices FCW<br />
1/03/50 Magnetic storage system for electronic binary digital computers FCW, JCW<br />
<br />
The identification and bio notes for the inventors in the above Table are:<br />
Initials Name Relevant dates at Manchester University, status<br />
during period ending March ‘50, etc.<br />
DBGE Dai Edwards Sept. ’48 onwards; EE research student<br />
TK Tom Kilburn Dec. ’46 onwards; TRE employee, then EE lecturer<br />
MHAN Max Newman Oct. ’45 onwards; Professor of Maths<br />
AAR Alec Robinson April ’47 – April ’49; EE research student, then to Ferranti<br />
GET Tommy Thomas Sept. ’48 – Sept. ’55; EE research student<br />
GCT Geoff Tootill Sept. ’47 – Nov. 49; TRE employee, then to Ferranti<br />
JCW Cliff West Oct. ’46 – Dec. ’57; EE research student, then assistant lecturer<br />
FCW FC (or Freddie) Williams Dec. ’46 onwards; Professor of EE<br />
<br />
<br />
The first widely-circulated report describing the Williams/Kilburn storage technology was:<br />
3 (b). T Kilburn, A storage system for use with binary digital computing machines. Typed foolscap report dated 1st December 1947, consisting of 52 pages of text, 32 pages of diagrams and one page with three photos. This report was produced for the Telecommunications Research Establishment (TRE). At the time Kilburn was on secondment from TRE, working with Professor F C Williams in the Electro-technics Department at Manchester University. It is known that several copies of this Report were taken to the USA in the spring of 1948 by Douglas Hartree (Cambridge University), Harold Huskey (SWAC at UCLA) and A M Uttley (TRE).<br />
<br />
The first paper to appear in a scientific journal was:<br />
3 (c). F C Williams & T Kilburn, A storage system for use with binary digital computing machines. Proc. IEE, Vol. 96, part 2, No. 30, 1949, pages 183 ff.<br />
<br />
4. Jan Rajchman, The Selective Electrostatic Storage Tube. RCA Review, Volume 12, No. 1, pp 53 - 97, March 1951.<br />
<br />
5 (a). The idea of index registers, initially called B lines on the Manchester University computer, arose between 15th July and 13th October 1948. Evidence comes from G C Tootill’s laboratory notebook, which is preserved as item NAHC/MUC/2/C3 in the National Archive for the History of Computing in Manchester. Working B line hardware was in use on the computer by April 1949. The relevant UK Patent was filed on 3rd June 1949 – see list in ref. 3(a) above. <br />
<br />
5 (b). The first paper to appear in a scientific journal that mentions the modifier registers is: T Kilburn, The University of Manchester universal high speed digital computing machine. Nature, Vol. 164, Oct. 1949, pages 684 – 691. <br />
<br />
6. The full text of the 26th October 1948 letter sent by Sir Ben Lockspeiser to Eric Grundy, Manager of Ferranti’s Instrument Department at Moston, Manchester, reads as follows:<br />
Dear Mr Grundy,<br />
I saw Mr Barton [MOS] yesterday morning and told him of the arrangements I made <br />
with you at Manchester University. I have instructed him to get in touch with your <br />
firm and draft and issue a suitable contract to cover these arrangements.<br />
You may take this letter as authority to proceed on the lines we discussed, namely, <br />
to construct an electronic calculating machine to the instructions of Professor F C <br />
Williams.<br />
I am glad we were able to meet with Professor Williams as I believe that the making <br />
of electronic calculating machines will become a matter of great value and importance.<br />
Please let me know if you meet with any difficulties”. <br />
<br />
7. S H Lavington, Early computing in Britain: Ferranti Ltd. and government funding, 1948 – 1958. Published by Springer, 2019. ISBN: 978-3-030-15102-7.<br />
<br />
8. R A (Tony) Brooker, who took over from Alan Turing in October 1951 as leader of the systems software support for the Ferranti Mark I, developed a high-level language (an Autocode) for the computer:<br />
<br />
8 (a). R A Brooker, An attempt to simplify coding for the Manchester computer. British Journal of Applied Physics, Vol. 6, September 1955, pages 307 – 311.<br />
<br />
8 (b). M Campbell-Kelly, Programming the Mark I: early programming activity at the University of Manchester. Annals of the History of Computing, Vol. 2 no. 2 April 1980, pages 130 – 168.<br />
<br />
The Mark I Autocode avoided three difficulties facing all early programmers:<br />
(i) the awkward machine code in which programs had to be written, making <br />
software difficult to update and adapt;<br />
(ii) the necessity for the user to frequently swap information between the fast (but <br />
small) primary memory and the slow (but large) secondary memory during run time;<br />
(iii) scaling and precision: the need to be aware of the limited number-range of <br />
fixed-point and to perform most scientific and engineering calculations in <br />
floating-point arithmetic, for which there was no hardware support.<br />
<br />
The Mark I Autocode is best introduced by a short sequence which prints the root mean square (RMS) of the floating-point variables v1, v2, … v100.<br />
n1 = 1<br />
v101 = 0<br />
2v102 = vn1 x vn1<br />
v101 = v101 + v102<br />
n1 = n1 + 1<br />
j2, 100 ≥ n1<br />
v101 = v101/100.0<br />
*v101 = F1(v101)<br />
<br />
The 5-track paper tape for this sequence would have been prepared on a special teleprinter in the Computing Machine Laboratory which had been adapted with appropriate printable symbols (illustrated here in the type font Times New Roman). In the Autocode convention, n1 is an integer and v1 etc are floating-point numbers. The symbol * causes the printing of a variable to ten decimal places on a new line and F1 signifies the intrinsic function square root. <br />
<br />
The Autocode was released to users in March 1954, a year or two ahead of the American Fortran developments. Autocodes were developed for a range of British computers by Ferranti Ltd., Elliott Automation Ltd. and ICT. By 1961 the world-wide proliferation of high-level languages had led the Manchester team to develop the Compiler Compiler [ref. 9 (a, b, c)], another software landmark. <br />
<br />
9 (a). The basis for the Compiler Compiler was first described in:<br />
R A Brooker & D Morris, An assembly program for a phrase structure language. Computer Journal, Vol. 3(1960), page 168.<br />
<br />
9 (b). A number of UK-based papers followed but the developments did not come to universal attention until this publication:<br />
S Rosen, A Compiler-Building System Developed by Brooker and Morris. Comm. A.C.M., Vol. 7, No. 7, July 1964, pages 403 - 414. <br />
<br />
9 (c). The history of the Compiler Compiler development, including a retrospective Appendix by Tony Brooker, is presented here: <br />
S H Lavington and others: Tony Brooker and the Atlas Compiler Compiler. February 2014 & revised April 2016: <br />
http://curation.cs.manchester.ac.uk/atlas/elearn.cs.man.ac.uk/_atlas/docs/Tony%20Brooker%20and%20the%20Atlas%20Compiler%20Compiler.pdf <br />
<br />
10. The outgoing Professor Willis Jackson and his research group quit the Department of Electro-Technics in September 1946. This left the Electro-Technics Department severely depleted and especially so in the area of electronics. Albert Cooper, the Department’s Chief Technician, was reported to be “disgusted” with Jackson’s move because it seemed to him that “the whole of the Department was disappearing into Jackson’s van”. The full history is recounted in: Electrical Engineering at Manchester University; the story of 125 years of achievement. T E Broadbent. Published by The Manchester School of Engineering, University of Manchester, 1998. ISBN 0 – 9531203 – 0 – 9. <br />
<br />
11. On 19th and 22nd August 1949 F C Williams gave two lectures in Canada at the National Research Council’s Atomic Energy project, Research Division, Chalk River, Ontario. These lectures were typed up from a wire recording and bound as Report LT-24, 14th Sept. 1949, High speed universal digital computers. (28 typed pages and 16 figures). This Report essentially describes the Williams CRT storage system, the SSEM computer and the June 1948 factoring program. Report LT-24 is preserved as item NAHC/MUC/1/D5 at the National Archive for the History of Computing in Manchester. <br />
<br />
12. It is clear that Max Newman intended to acquire a computer rather than designing and building one himself. Surviving records are sparse but Jack Good kept notes from which it seems that the Manchester mathematicians favoured a machine based on von Neumann’s IAS project at Princeton rather than on Alan Turing’s ACE project at NPL. In the event, a Pilot version of the ACE computer did not run a program at NPL until May 1950 and the IAS computer did not work at Princeton until early 1951. Good’s notes are available as follows:<br />
Early Notes on Electronic Computers. I J Good. 78 typed and hand-written pages mostly covering the period 1947-8, with Good’s retrospective introduction dated 23rd March 1972, and Good’s covering letter to Simon Lavington dated 7th April 1976. Catalogue NAHC/MUC/2/A4 in the National Archive for the History of Computing. An analysis of Good’s notes is given in reference 7 above.<br />
<br />
13. F C Williams & T Kilburn, The University of Manchester computing machine. Inaugural conference of the Manchester University computer, July 1951, pages 5 – 11. This paper was also presented at the Joint AIEE/IRE Computer Conference, Philadelphia, December 1951. This illustrated paper describes the progression from the 1948 SSEM (Baby) computer, via 1949 enhancements, to the final commercial version known as the Ferranti Mark I. A pdf of this paper is attached.<br />
<br />
14 (a). B W Pollard & K Lonsdale, The construction and operation of the Manchester University computer. Proc IEE, Vol. 100, part 2, 1953, pages 501 – 512. A pdf of this paper is attached. See also Fig. 5 in the accompanying collection of images.<br />
<br />
14 (b). T Kilburn, G C Tootill, D B G Edwards & B W Pollard, Digital computers at Manchester University. Proc. IEE, Vol. 100, part 2, 1953, pages 487 – 500.<br />
<br />
<br />
<br />
<br />
Supporting materials:<br />
1. Pdf of a letter dated 29th September 2020 from the University of Manchester regarding the installation of an IEEE Milestone plaque. [[Media:Baby_Plaque_UoM_letter.pdf]]<br />
2. Word document containing seven photographs plus explanations. [[Media:BabyPhotosV2.doc]]<br />
3. Pdf of reference [13], the paper presented by F C Williams and T Kilburn at the July 1951 Inaugural Conference of the Ferranti Mark I computer. [[Media:Inaug Conf Ref 13.pdf]]<br />
4. Pdf of reference 14(a), the Proc. IEE paper by Pollard and Lonsdale. [[Media:IEE_Pollard_Lonsdale_19530146.pdf]]<br />
|submitted=Yes<br />
}}</div>Administrator1http://ieeemilestones.ethw.org/index.php?title=Milestone-Proposal:The_Ferranti_%27Baby%27;_Small-Scale_Experimental_Machine_(SSEM)&diff=9864Milestone-Proposal:The Ferranti 'Baby'; Small-Scale Experimental Machine (SSEM)2021-01-19T13:59:06Z<p>Administrator1: Administrator1 moved page Milestone-Proposal:The Ferranti 'Baby'; Small-Scale Experimental Machine (SSEM) to Milestone-Proposal:The Manchester University 'Baby' computer; Small-Scale Experimental Machine (SSEM)</p>
<hr />
<div>#REDIRECT [[Milestone-Proposal:The Manchester University 'Baby' computer; Small-Scale Experimental Machine (SSEM)]]</div>Administrator1http://ieeemilestones.ethw.org/index.php?title=Milestone-Proposal:Intel_4004_Microprocessor&diff=9571Milestone-Proposal:Intel 4004 Microprocessor2020-10-12T19:40:26Z<p>Administrator1: </p>
<hr />
<div>{{Proposal<br />
|docketid=2020-04<br />
|litigation=No<br />
|more than 25 years=Yes<br />
|within fields of interest=Yes<br />
|benefit to humanity=Yes<br />
|regional importance=Yes<br />
|ou is paying=Yes<br />
|ou is arranging dedication=Yes<br />
|section is taking responsibility for plaque=Yes<br />
|a11=Yes<br />
|a3=1971<br />
|a1=Intel 4004 Microprocessor, 1971<br />
|plaque citation=The Intel 4004 microprocessor incorporated a 4-bit computer's Central Processing Unit (CPU). Its new silicon-gate MOS fabrication enabled a single-chip design with significant cost and performance improvements over existing multi-chip designs. Although initially created for a family of calculating machines, its general-purpose instruction set allowed software customization. The single-chip 4004 created the industry model for the microprocessor — a key driver of the digital information age.<br />
|a2b=Santa Clara Valley<br />
|IEEE units paying={{IEEE Organizational Unit Paying<br />
|Unit=Santa Clara Valley<br />
|Senior officer name=Taylor Winship<br />
|Senior officer email=taylor_winship@att.net<br />
}}<br />
|IEEE units arranging={{IEEE Organizational Unit Arranging<br />
|Unit=Santa Clara Valley<br />
|Senior officer name=Taylor Winship<br />
|Senior officer email=taylor_winship@att.net<br />
}}<br />
|IEEE sections monitoring={{IEEE Section Monitoring<br />
|Section=Santa Clara Valley<br />
|Section chair name=Tayor Winship<br />
|Section chair email=taylor_winship@att.net<br />
}}<br />
|Milestone proposers={{Milestone proposer<br />
|Proposer name=David Laws<br />
|Proposer email=laws@computerhistory.org<br />
}}{{Milestone proposer<br />
|Proposer name=Brian Berg<br />
|Proposer email=brianberg@gmail.com<br />
}}<br />
|a2a=Robert N. Noyce Building (Intel's Headquarters), 2200 Mission College Blvd, Santa Clara, CA 95054 USA 37.3882663, -121.9637798<br />
|a7=By the entrance to the Intel Museum, which is accessible from the ground floor lobby of the Robert N. Noyce Building (Intel's Headquarters).<br />
|a8=The 4004 development work was performed at Intel's original headquarters at 365 E. Middlefield Rd., Mountain View, CA, which is not extant. The engineering design team moved to Intel's new headquarters at 3065 Bowers Ave., Santa Clara, CA (later called Santa Clara 1, or "SC1") in 1971, prior to the November 1971 product launch. This left only the Fab 1 facility in Mountain View, where the MCS-4 Micro Computer Chip Set was manufactured for at least its first year of production. SC1 is extant and retains the SC1 designation, is no longer Intel's Headquarters, and is not accessible to the public. SC1 is 2.1 miles from the Intel Museum site.<br />
|mounting details=Indoors in a location adjoining the Intel Museum's entrance.<br />
|a9=The Intel Museum is open to the public during normal business hours. There is no charge for entry.<br />
|a10=Intel Corporation<br />
|a4=The Intel 4004 was a complete 4-bit parallel central processing unit (CPU) on a single silicon chip. Introduced in 1971 as a member of the MCS-4 Micro Computer Chip Set, it was the first commercial microprocessor integrated circuit offered to the general public. The success of the product established the commercial viability of the microprocessor concept, led to the development of 8-bit chips from Intel and other vendors, and also led to the use of microprocessors first in embedded products, personal computers, and then throughout the industry. Single-chip microprocessors are now ubiquitous throughout the world.<br><br />
<br><br />
Development work began in 1969 when Japanese calculator-maker Busicom asked Intel to design a set of chips for a family of calculating machines. The original design called for seven custom chips, out of which small computers based on ROM and shift register read-write memory could be built. Three of the seven chips were intended to perform the function of a CPU optimized for a variety of calculating machines. Ted Hoff saw the opportunity to simplify this approach by using dynamic RAM memory then in development at Intel. His proposed solution was an architecture for a single-chip, general-purpose CPU and three companion chips for memory and I/O.<br><br />
<br><br />
As described in the [https://www.computerhistory.org/siliconengine/silicon-gate-technology-developed-for-ics/ Computer History Museum's 1968: SILICON GATE TECHNOLOGY DEVELOPED FOR ICS webpage], Federico Faggin developed enhancements to MOS technology that allowed the general-purpose processor that was being developed under contract to Busicom to be miniaturized enough so as to fit onto a single chip: "Intel pursued silicon-gate as the primary technology for semiconductor memories as it delivered 3 to 5 times faster speed in half the chip area of conventional MOS. Intel's first commercial MOS device, the 1101 256-bit RAM, was introduced in 1969. Faggin joined Intel in 1970. By adding a buried contact and other process enhancements for logic applications he was able to design the 4004 microprocessor CPU to fit on a manufacturable die size." This is further described in the [https://www.computerhistory.org/siliconengine/microprocessor-integrates-cpu-function-onto-a-single-chip/ Computer History Museum's 1971: MICROPROCESSOR INTEGRATES CPU FUNCTION ONTO A SINGLE CHIP webpage].<br><br />
<br><br />
Cognizant of financial troubles at Busicom, and sensing the market potential of the product, Intel made what was perhaps the most important decision in the history of the company: they returned their $60,000 design fee to Busicom and agreed to sell them the chip set at a lower cost in exchange for Busicom's surrendering of its exclusive rights. Now with its complete ownership, Intel introduced the chip set to the world in November 1971 with an advertisement that touted "Announcing a new era of integrated electronics: A micro-programmable computer on a chip!"<br><br />
<br><br />
Because electronic designers had never before had the ability to design a new compact computerized product with such a small set of chips while using software to quickly tailor and fine-tune its capabilities, an extensive campaign to educate the engineering community about the MCS-4 chip family was necessary. An important part of the campaign included educating engineers about the software since this was a requirement that was new for a hardware engineering team. In addition, as no high-level language compilers were available for the 4004 chip, the software needed to be written in assembly language. After a slow start, the chip family began to find a home in control applications that included traffic lights and taxi meters. While these initial usages were relatively unsophisticated, they had a small footprint, were created at a low cost, and could be easily tweaked with software - and they were the start of a new realm of computerized products.<br />
|a6=The key technical obstacle was adapting Intel's P-channel silicon-gate MOS process to accommodate 2300 transistors in a chip size that was economical and practical to manufacture in volume. As discussed with reference to Federico Faggin in the [[Media:Ref1-Electronics MOS-Story(29-Sept-1969).pdf|29 Sept 1969 issue of <i>Electronics</i>]], the new direction in MOS technology at that time was the development of a self-aligned gate MOS process (to reduce parasitic capacitances) combined with a lower power supply voltage (from -24 volts to -15 volts) by reducing the maximum threshold voltage from -9 volts to -3.5 volts. This was accomplished for the first time in 1968 by using polysilicon instead of aluminum in the gate electrode. The result was a technology that, for the same power dissipation, resulted in (1) a 5x speed improvement, (2) reduced leakage current (by more than 100 times), (3) higher circuit density (especially for random logic designs) using the buried contact, which allowed fabricating an insulated contact between junctions and polysilicon, thereby resulting in half the chip area for the same function, and (4) higher reliability by using phosphorus gettering to reduce metal impurities, which was not possible with an aluminum gate. This increase in speed and functionality within a single chip allowed the 4004 to be a single-chip CPU, with a resultant improved cost and greatly improved performance, as compared with a multi-chip implementation.<br><br />
<br><br />
The MCS-4 family consisted of: 4001 (ROM), 4002 (RAM), 4003 (Shift Register) and 4004 (CPU), and each device had a pin count of only 16. While this low pin count reduced manufacturing cost, it also necessitated a cumbersome 4-bit bi-directional data bus for the communication of 12-bit addresses and 8-bit instructions amongst these 4 devices, a scheme implemented using time-division multiplexing and a fixed 8-click time clock in which each of the 8 clicks had an agreed direction and purpose, and as further described in [https://patentimages.storage.googleapis.com/7e/e8/25/605e0d53b55b6c/US3821715.pdf U.S. Patent 3,821,715]. While performance thereby suffered by a factor of 2.5, the 5x speed and 2x size improvements enabled by the use of silicon-gate MOS technology (which also allowed the chip to be small enough to fit into a 16-pin package) resulted in a family of devices whose overall system functionality was not impaired. A similar approach was applied to the 18-pin 8008 (introduced in 1972), sacrificing speed and requiring 35 external ICs to interface the chip to memory and I/O. Using a 40-pin package, Intel's highly successful 8080 microprocessor finally replaced the 8008 in 1974.<br><br />
<br><br />
The political and commercial obstacles at the time included initial reluctance by Intel management to promote a chip that would compete with products from the company’s existing customers, the reluctance of the market to grasp the power inherent in a single-chip CPU, and the lack of knowledge regarding how to use such a device. The latter two obstacles were overcome by way of extensive customer education programs, and new hardware and software development tools.<br />
|a5=By the late 1960s, designers were striving to integrate the CPU functions of a computer onto a handful of MOS LSI chips. Two notable examples are (1) in 1969, Lee Boysel created the Four-Phase Systems Inc. AL-1, an 8-bit CPU slice that was expandable to 32 bits, and (2) in 1970, Steve Geller and Ray Holt of Garrett AiResearch designed the MP944 20-bit chip set to implement the F-14A Central Air Data Computer on six chips. Both were multi-chip custom designs for specific applications.<br><br />
<br><br />
David Laws, Semiconductor Curator at the Computer History Museum, wrote a 2018 essay titled [https://computerhistory.org/blog/who-invented-the-microprocessor/ Who Invented the Microprocessor?] in which he states "This article describes a chronology of early approaches to integrating the primary building blocks of a computer on to fewer and fewer microelectronic chips, culminating in the concept of the microprocessor." His treatise describes how the single-chip 4004 microprocessor was preceded by a number of other devices that incorporated variations of a microprocessor device, but which were all multi-chip implementations.<br><br />
<br><br />
The Intel 4004 was a general-purpose device that integrated more of the essential logical elements of a processor onto a single chip than what had been done previously. These functions included a program counter, instruction decode/control logic, the ALU, data registers, and the data path between these elements. Although originally designed to implement a family of programmable calculating machines by way of Intel's contract with the Japanese company Busicom, the 4004's general-purpose instruction set allowed it to be embedded in devices such as peripherals, terminals, process controllers, and test and measurement systems.<br />
|references=1. HONORS<br><br />
[https://marconisociety.org/fellows/federico-faggin/ The Marconi Society's 1988 <b>Marconi Prize</b> to Federico Faggin "for his pioneering contributions to the implementation of the microprocessor, a principal building block of modern telecommunications" ].<br><br />
The 1988 <b>Gold Medal for Science and Technology</b> to Federico Faggin from the Italian Prime Minister.<br><br />
[https://www.computer.org/profiles/federico-faggin The 1994 IEEE Computer Society's <b>W. Wallace McDowell Award</b> to Federico Faggin “for the development of the Silicon Gate Process, and the first commercial microprocessor” ].<br><br />
[https://www.invent.org/inductees/federico-faggin The 1996 <b>National Inventors Hall of Fame</b> inductees included Federico Faggin], [https://www.invent.org/inductees/marcian-e-ted-hoff Marcian E. (Ted) Hoff] and [https://www.invent.org/inductees/stanley-mazor Stanley Mazor, for the microprocessor].<br><br />
The 1997 <b>Kyoto Prize</b> recipients included [https://www.kyotoprize.org/en/laureates/federico_faggin/ Federico Faggin], [https://www.kyotoprize.org/en/laureates/marcian_edward_hoff_jr/ Marcian Edward Hoff, Jr. ], [https://www.kyotoprize.org/en/laureates/stanley_mazor/ Stanley Mazor] and [https://www.kyotoprize.org/en/laureates/masatoshi_shima/ Masatoshi Shima] in Advanced Technology: Electronics.<br><br />
[https://www.semiconductors.org/news-events/awards/ The 2000 <b>Robert N. Noyce Award</b> presented by the Semiconductor Industry Association to Federico Faggin, Stanley Mazor and Ted Hoff, "Inventors of the Microprocessor" ].<br><br />
[https://computerhistory.org/press-releases/2009-Fellow-Awards-Honorees/ The 2009 <b>Computer History Museum Fellows</b> included Federico Faggin, Marcian Edward "Ted" Hoff, Stan Mazor and Masatoshi Shima "for their work on the Intel 4004, the world’s first commercial microprocessor" ].<br><br />
The 2009 <b>National Medal of Technology and Innovation</b> recipients [https://www.uspto.gov/learning-and-resources/ip-programs-and-awards/national-medal-technology-and-innovation/recipients/2009 included Federico Faggin, Marcian E. Hoff, Jr. and Stanley Mazor, as presented by President Obama] "for the conception, design and application of the first microprocessor, which was commercially adopted and became the universal building block of digital electronic systems, significantly impacting the global economy and people's day-to-day lives".<br><br />
<br><br />
2. PATENTS RESULTING FROM 4004 DESIGN<br><br />
[https://patentimages.storage.googleapis.com/6b/d7/16/e26a04b80c6eb6/US3753011.pdf Faggin, F. “<b>Power supply settable bi-stable circuit</b>” U.S. Patent 3,753,011 ]<br><br />
[https://patentimages.storage.googleapis.com/7e/e8/25/605e0d53b55b6c/US3821715.pdf Hoff, Jr., M. E.; Mazor, Stanley; Faggin, Federico. "<b>Memory System for a Multi-Chip Digital Computer</b>" U.S. Patent 3,821,715 ]<br><br />
<br><br />
3. TECHNICAL ARTICLES, CONFERENCE PAPERS & BOOKS<br><br />
"<b>A faster generation of MOS devices with low thresholds is riding the crest of the new wave, silicon-gate IC's</b>," <i>Electronics</i> (29 Sept 1969) pp. 88-89.<br><br />
Faggin, F. and Hoff, M.E. "<b>Standard parts and custom design merge in four-chip processor kit</b>," <i>Electronics</i> (24 April 1972) pp. 112-116.<br><br />
Altman, Laurence "<b>Single Chip Microprocessors open up a New World of Applications</b>," <i>Electronics</i> (18 April 1974) pp. 81-87.<br><br />
Noyce, R., and Hoff, M. "<b>A History of Microprocessor Development at Intel</b>," <i>IEEE Micro</i>, Vol. 1, No. 1 (1981) pp. 8-21.<br><br />
Faggin, F.; Hoff, M.E., Jr.; Mazor, S.; Shima, M. "<b>The history of the 4004</b>," <i>IEEE Micro</i>, Vol. 16, Issue 6 (December 1996) pp. 10-20.<br><br />
Faggin, F., Shima, M., Hoff, M.E., Feeny, H., Mazor S. "<b>The MCS4 - An LSI micro-computer system</b>," IEEE 1972 Region Six Conference, IEEE Press (1972) pp. 8-11.<br><br />
<b>[[Media:Ref2-Intel MCS-4 DataSheet.pdf|Intel MCS-4 Micro Computer Set</b> Data Sheet, 1971 (12 pages).]]<br><br />
[[Media:Ref3-AugartenBookExcerpt.pdf|Augarten, Stan. "<b>The First Microprocessor - 4004</b>,"]] <i>State Of The Art: A Photographic History of the Integrated Circuit</i>, New Haven & New York: Ticknor and Fields, 1983, pp. 30-31.<br><br />
Malone, Michael S. "<b><i>The Microprocessor: A Biography</i></b>," New York: Springer-Verlag TELOS, 1995, pp. 3-20.<br><br />
<br><br />
4. INTERVIEWS & ORAL HISTORIES<br><br />
[https://ethw.org/Oral-History:Federico_Faggin <b>Federico Faggin: An Interview Conducted by John Vardalas</b>, IEEE History Center Interview #442, 27 May 2004].<br><br />
[https://archive.computerhistory.org/resources/access/text/2012/07/102658025-05-01-acc.pdf <b>Federico Faggin Oral History</b>, interviewed by Gardner Hendrie (22 Sept 2004, 13 Dec 2004 and 3 March 2005), Computer History Museum Catalog # 102658025 ].<br><br />
[https://archive.computerhistory.org/resources/access/text/2012/08/102657974-05-01-acc.pdf <b>Ted Hoff and Stan Mazor on their contributions to the Intel 4004</b>, Ted Hoff and Stan Mazor interviewed by David Laws (20 Sept 2006), Computer History Museum Catalog #102657974 ]<br><br />
[https://archive.computerhistory.org/resources/access/text/2012/04/102658187-05-01-acc.pdf <b>Oral History Panel on the Development and Promotion of the Intel 4004 Microprocessor</b>, Federico Faggin, Hal Feeney, Ted Hoff, Stan Mazor and Masatoshi Shima, interviewed by Dave House, and edited by David Laws (25 April 2007), Computer History Museum Catalog #102658187 ]<br><br />
<br><br />
5. ONLINE VIDEOS<br><br />
[https://www.youtube.com/watch?v=y0TPWoJGv-E <b>The Designer Behind the First Microprocessor: Federico Faggin</b> ] (length: 4:19)<br><br />
[https://www.youtube.com/watch?v=7MgHsgoilQ4 <b>Ted Hoff, Inventor of the Microprocessor</b>, Richard Newton Distinguished Innovator Lecture Series, U.C. Berkeley (8 Sept 2009) ] (length: 48:08)<br><br />
[https://www.youtube.com/watch?v=j00AULJLCNo <b>Intel 4004 Microprocessor 35th Anniversary</b>, Computer History Museum (13 Nov 2006) ] (length: 1:37:59)<br><br />
'''[https://www.computerhistory.org/revolution/digital-logic/12/285/2285 The Story of the Intel 4004]''', Computer History Museum: Collection of video excerpts of Ted Hoff, Masatoshi Shima, Stan Mazor, Federico Faggin and Dave House (3:08) <br><br />
'''[https://youtu.be/k_zl4AhPtz0 Intel Presents "The MCS-4 Story]":''' Abbreviated version of an Intel video shown as a 16mm film at seminars across the U.S.; narrated by Ted Hoff, with video assistance by Stan Mazor; the full version included technical details such as how a 4004 jump instruction was fetched and executed (2:19)<br><br />
<br><br />
6. BLOG, PHOTOS & MISC. DOCUMENTS<br><br />
[https://computerhistory.org/blog/who-invented-the-microprocessor/ <b>Who Invented the Microprocessor?</b>, David Laws (20 Sept 2018) ].<br><br />
[https://newsroom.intel.com/editorials/intel-a-look-back-on-the-early-years/ <b>Intel: A Look Back on the Early Years</b>: Photos from Intel in the Early 1970s ].<br><br />
[https://www.intel.com/content/www/us/en/history/history-1988-annual-report.html <b>Intel 1988 Annual Report</b>: Includes historical outline and photos from Intel's first 20 years ].<br><br />
[https://www.computerhistory.org/collections/catalog/102635152 <b>Photo of 4004 die</b> ].<br><br />
[https://www.computerhistory.org/siliconengine/microprocessor-integrates-cpu-function-onto-a-single-chip/ <b>1971: Microprocessor Integrates CPU Function on to a Single Chip - Silicon-Gate Process Technology and Design Advances Squeeze Computer Central Processing Units (CPU) Onto Single Chips</b>, <i>The Silicon Engine</i> (30 May 2020) (includes a plethora of links, photos and citations related to the 4004, along with a nice overview) ].<br><br />
[https://www.intel-vintage.info/apps/blog/ <b>Unofficial Intel Archives Website</b>: photos, annual reports, software, documentation, etc. ].<br><br />
[https://www.computerhistory.org/revolution/digital-logic/12/285/1534 '''Busicom 141-PF Printing Calculator Engineering Prototype, 1971'''], Computer History Museum: Engineering prototype of the successful test bed for the first commercial application of the Intel 4004<br><br />
<br><br />
7. VIDEODISC<br><br />
[https://searchworks.stanford.edu/view/6964777 <b>The Microprocessor Chronicles: The History of the Microprocessor</b> "The history of the invention of the microprocessors through three and half decades of technological change as told by those that made it happen. Interviews with Dennis Carter, Federico Faggin, John Hennessy, Ted Hoff, Dave House, Stan Mazor, Regis McKenna, Gordon Moore, Jerrt Sanders, Albert Yu," Stanford University Library; Palo Alto, CA, 2005 ]<br />
|submitted=Yes<br />
}}</div>Administrator1http://ieeemilestones.ethw.org/index.php?title=Milestone-Proposal:Intel_4004_Microprocessor&diff=9570Milestone-Proposal:Intel 4004 Microprocessor2020-10-12T19:39:47Z<p>Administrator1: </p>
<hr />
<div>{{Proposal<br />
|docketid=2020-04<br />
|litigation=No<br />
|more than 25 years=Yes<br />
|within fields of interest=Yes<br />
|benefit to humanity=Yes<br />
|regional importance=Yes<br />
|ou is paying=Yes<br />
|ou is arranging dedication=Yes<br />
|section is taking responsibility for plaque=Yes<br />
|a11=Yes<br />
|a3=1971<br />
|a1=Intel 4004 Microprocessor, 1971<br />
|plaque citation=The Intel 4004 microprocessor incorporated a 4-bit computer's Central Processing Unit (CPU). Its new silicon-gate MOS fabrication enabled a single-chip design with significant cost and performance improvements over existing multi-chip designs. Although initially created for a family of calculating machines, its general-purpose instruction set allowed software customization. The single-chip 4004 created the industry model for the microprocessor — a key driver of the digital information age.<br />
|a2b=Santa Clara Valley<br />
|IEEE units paying={{IEEE Organizational Unit Paying<br />
|Unit=Santa Clara Valley<br />
|Senior officer name=Taylor Winship<br />
|Senior officer email=taylor_winship@att.net<br />
}}<br />
|IEEE units arranging={{IEEE Organizational Unit Arranging<br />
|Unit=Santa Clara Valley<br />
|Senior officer name=Taylor Winship<br />
|Senior officer email=taylor_winship@att.net<br />
}}<br />
|IEEE sections monitoring={{IEEE Section Monitoring<br />
|Section=Santa Clara Valley<br />
|Section chair name=Tayor Winship<br />
|Section chair email=taylor_winship@att.net<br />
}}<br />
|Milestone proposers={{Milestone proposer<br />
|Proposer name=David Laws<br />
|Proposer email=laws@computerhistory.org<br />
}}{{Milestone proposer<br />
|Proposer name=Brian Berg<br />
|Proposer email=brianberg@gmail.com<br />
}}<br />
|a2a=Robert N. Noyce Building (Intel's Headquarters), 2200 Mission College Blvd, Santa Clara, CA 95054 USA 37.3882663, -121.9637798<br />
|a7=By the entrance to the Intel Museum, which is accessible from the ground floor lobby of the Robert N. Noyce Building (Intel's Headquarters).<br />
|a8=The 4004 development work was performed at Intel's original headquarters at 365 E. Middlefield Rd., Mountain View, CA, which is not extant. The engineering design team moved to Intel's new headquarters at 3065 Bowers Ave., Santa Clara, CA (later called Santa Clara 1, or "SC1") in 1971, prior to the November 1971 product launch. This left only the Fab 1 facility in Mountain View, where the MCS-4 Micro Computer Chip Set was manufactured for at least its first year of production. SC1 is extant and retains the SC1 designation, is no longer Intel's Headquarters, and is not accessible to the public. SC1 is 2.1 miles from the Intel Museum site.<br />
|mounting details=Indoors in a location adjoining the Intel Museum's entrance.<br />
|a9=The Intel Museum is open to the public during normal business hours. There is no charge for entry.<br />
|a10=Intel Corporation<br />
|a4=The Intel 4004 was a complete 4-bit parallel central processing unit (CPU) on a single silicon chip. Introduced in 1971 as a member of the MCS-4 Micro Computer Chip Set, it was the first commercial microprocessor integrated circuit offered to the general public. The success of the product established the commercial viability of the microprocessor concept, led to the development of 8-bit chips from Intel and other vendors, and also led to the use of microprocessors first in embedded products, personal computers, and then throughout the industry. Single-chip microprocessors are now ubiquitous throughout the world.<br><br />
<br><br />
Development work began in 1969 when Japanese calculator-maker Busicom asked Intel to design a set of chips for a family of calculating machines. The original design called for seven custom chips, out of which small computers based on ROM and shift register read-write memory could be built. Three of the seven chips were intended to perform the function of a CPU optimized for a variety of calculating machines. Ted Hoff saw the opportunity to simplify this approach by using dynamic RAM memory then in development at Intel. His proposed solution was an architecture for a single-chip, general-purpose CPU and three companion chips for memory and I/O.<br><br />
<br><br />
As described in the [https://www.computerhistory.org/siliconengine/silicon-gate-technology-developed-for-ics/ Computer History Museum's 1968: SILICON GATE TECHNOLOGY DEVELOPED FOR ICS webpage], Federico Faggin developed enhancements to MOS technology that allowed the general-purpose processor that was being developed under contract to Busicom to be miniaturized enough so as to fit onto a single chip: "Intel pursued silicon-gate as the primary technology for semiconductor memories as it delivered 3 to 5 times faster speed in half the chip area of conventional MOS. Intel's first commercial MOS device, the 1101 256-bit RAM, was introduced in 1969. Faggin joined Intel in 1970. By adding a buried contact and other process enhancements for logic applications he was able to design the 4004 microprocessor CPU to fit on a manufacturable die size." This is further described in the [https://www.computerhistory.org/siliconengine/microprocessor-integrates-cpu-function-onto-a-single-chip/ Computer History Museum's 1971: MICROPROCESSOR INTEGRATES CPU FUNCTION ONTO A SINGLE CHIP webpage].<br><br />
<br><br />
Cognizant of financial troubles at Busicom, and sensing the market potential of the product, Intel made what was perhaps the most important decision in the history of the company: they returned their $60,000 design fee to Busicom and agreed to sell them the chip set at a lower cost in exchange for Busicom's surrendering of its exclusive rights. Now with its complete ownership, Intel introduced the chip set to the world in November 1971 with an advertisement that touted "Announcing a new era of integrated electronics: A micro-programmable computer on a chip!"<br><br />
<br><br />
Because electronic designers had never before had the ability to design a new compact computerized product with such a small set of chips while using software to quickly tailor and fine-tune its capabilities, an extensive campaign to educate the engineering community about the MCS-4 chip family was necessary. An important part of the campaign included educating engineers about the software since this was a requirement that was new for a hardware engineering team. In addition, as no high-level language compilers were available for the 4004 chip, the software needed to be written in assembly language. After a slow start, the chip family began to find a home in control applications that included traffic lights and taxi meters. While these initial usages were relatively unsophisticated, they had a small footprint, were created at a low cost, and could be easily tweaked with software - and they were the start of a new realm of computerized products.<br />
|a6=The key technical obstacle was adapting Intel's P-channel silicon-gate MOS process to accommodate 2300 transistors in a chip size that was economical and practical to manufacture in volume. As discussed with reference to Federico Faggin in the [[Media:Ref1-Electronics MOS-Story(29-Sept-1969).pdf|29 Sept 1969 issue of <i>Electronics</i>]], the new direction in MOS technology at that time was the development of a self-aligned gate MOS process (to reduce parasitic capacitances) combined with a lower power supply voltage (from -24 volts to -15 volts) by reducing the maximum threshold voltage from -9 volts to -3.5 volts. This was accomplished for the first time in 1968 by using polysilicon instead of aluminum in the gate electrode. The result was a technology that, for the same power dissipation, resulted in (1) a 5x speed improvement, (2) reduced leakage current (by more than 100 times), (3) higher circuit density (especially for random logic designs) using the buried contact, which allowed fabricating an insulated contact between junctions and polysilicon, thereby resulting in half the chip area for the same function, and (4) higher reliability by using phosphorus gettering to reduce metal impurities, which was not possible with an aluminum gate. This increase in speed and functionality within a single chip allowed the 4004 to be a single-chip CPU, with a resultant improved cost and greatly improved performance, as compared with a multi-chip implementation.<br><br />
<br><br />
The MCS-4 family consisted of: 4001 (ROM), 4002 (RAM), 4003 (Shift Register) and 4004 (CPU), and each device had a pin count of only 16. While this low pin count reduced manufacturing cost, it also necessitated a cumbersome 4-bit bi-directional data bus for the communication of 12-bit addresses and 8-bit instructions amongst these 4 devices, a scheme implemented using time-division multiplexing and a fixed 8-click time clock in which each of the 8 clicks had an agreed direction and purpose, and as further described in [https://patentimages.storage.googleapis.com/7e/e8/25/605e0d53b55b6c/US3821715.pdf U.S. Patent 3,821,715]. While performance thereby suffered by a factor of 2.5, the 5x speed and 2x size improvements enabled by the use of silicon-gate MOS technology (which also allowed the chip to be small enough to fit into a 16-pin package) resulted in a family of devices whose overall system functionality was not impaired. A similar approach was applied to the 18-pin 8008 (introduced in 1972), sacrificing speed and requiring 35 external ICs to interface the chip to memory and I/O. Using a 40-pin package, Intel's highly successful 8080 microprocessor finally replaced the 8008 in 1974.<br><br />
<br><br />
The political and commercial obstacles at the time included initial reluctance by Intel management to promote a chip that would compete with products from the company’s existing customers, the reluctance of the market to grasp the power inherent in a single-chip CPU, and the lack of knowledge regarding how to use such a device. The latter two obstacles were overcome by way of extensive customer education programs, and new hardware and software development tools.<br />
|a5=By the late 1960s, designers were striving to integrate the CPU functions of a computer onto a handful of MOS LSI chips. Two notable examples are (1) in 1969, Lee Boysel created the Four-Phase Systems Inc. AL-1, an 8-bit CPU slice that was expandable to 32 bits, and (2) in 1970, Steve Geller and Ray Holt of Garrett AiResearch designed the MP944 20-bit chip set to implement the F-14A Central Air Data Computer on six chips. Both were multi-chip custom designs for specific applications.<br><br />
<br><br />
David Laws, Semiconductor Curator at the Computer History Museum, wrote a 2018 essay titled [https://computerhistory.org/blog/who-invented-the-microprocessor/ Who Invented the Microprocessor?] in which he states "This article describes a chronology of early approaches to integrating the primary building blocks of a computer on to fewer and fewer microelectronic chips, culminating in the concept of the microprocessor." His treatise describes how the single-chip 4004 microprocessor was preceded by a number of other devices that incorporated variations of a microprocessor device, but which were all multi-chip implementations.<br><br />
<br><br />
The Intel 4004 was a general-purpose device that integrated more of the essential logical elements of a processor onto a single chip than what had been done previously. These functions included a program counter, instruction decode/control logic, the ALU, data registers, and the data path between these elements. Although originally designed to implement a family of programmable calculating machines by way of Intel's contract with the Japanese company Busicom, the 4004's general-purpose instruction set allowed it to be embedded in devices such as peripherals, terminals, process controllers, and test and measurement systems.<br />
|references=1. HONORS<br><br />
[https://marconisociety.org/fellows/federico-faggin/ The Marconi Society's 1988 <b>Marconi Prize</b> to Federico Faggin "for his pioneering contributions to the implementation of the microprocessor, a principal building block of modern telecommunications" ].<br><br />
The 1988 <b>Gold Medal for Science and Technology</b> to Federico Faggin from the Italian Prime Minister.<br><br />
[https://www.computer.org/profiles/federico-faggin The 1994 IEEE Computer Society's <b>W. Wallace McDowell Award</b> to Federico Faggin “for the development of the Silicon Gate Process, and the first commercial microprocessor” ].<br><br />
[https://www.invent.org/inductees/federico-faggin The 1996 <b>National Inventors Hall of Fame</b> inductees included Federico Faggin], [https://www.invent.org/inductees/marcian-e-ted-hoff Marcian E. (Ted) Hoff] and [https://www.invent.org/inductees/stanley-mazor Stanley Mazor, for the microprocessor].<br><br />
The 1997 <b>Kyoto Prize</b> recipients included [https://www.kyotoprize.org/en/laureates/federico_faggin/ Federico Faggin], [https://www.kyotoprize.org/en/laureates/marcian_edward_hoff_jr/ Marcian Edward Hoff, Jr. ], [https://www.kyotoprize.org/en/laureates/stanley_mazor/ Stanley Mazor] and [https://www.kyotoprize.org/en/laureates/masatoshi_shima/ Masatoshi Shima] in Advanced Technology: Electronics.<br><br />
[https://www.semiconductors.org/news-events/awards/ The 2000 <b>Robert N. Noyce Award</b> presented by the Semiconductor Industry Association to Federico Faggin, Stanley Mazor and Ted Hoff, "Inventors of the Microprocessor" ].<br><br />
[https://computerhistory.org/press-releases/2009-Fellow-Awards-Honorees/ The 2009 <b>Computer History Museum Fellows</b> included Federico Faggin, Marcian Edward "Ted" Hoff, Stan Mazor and Masatoshi Shima "for their work on the Intel 4004, the world’s first commercial microprocessor" ].<br><br />
The 2009 <b>National Medal of Technology and Innovation</b> recipients [https://www.uspto.gov/learning-and-resources/ip-programs-and-awards/national-medal-technology-and-innovation/recipients/2009 included Federico Faggin, Marcian E. Hoff, Jr. and Stanley Mazor, as presented by President Obama] "for the conception, design and application of the first microprocessor, which was commercially adopted and became the universal building block of digital electronic systems, significantly impacting the global economy and people's day-to-day lives".<br><br />
<br><br />
2. PATENTS RESULTING FROM 4004 DESIGN<br><br />
[https://patentimages.storage.googleapis.com/6b/d7/16/e26a04b80c6eb6/US3753011.pdf Faggin, F. “<b>Power supply settable bi-stable circuit</b>” U.S. Patent 3,753,011 ]<br><br />
[https://patentimages.storage.googleapis.com/7e/e8/25/605e0d53b55b6c/US3821715.pdf Hoff, Jr., M. E.; Mazor, Stanley; Faggin, Federico. "<b>Memory System for a Multi-Chip Digital Computer</b>" U.S. Patent 3,821,715 ]<br><br />
<br><br />
3. TECHNICAL ARTICLES, CONFERENCE PAPERS & BOOKS<br><br />
"<b>A faster generation of MOS devices with low thresholds is riding the crest of the new wave, silicon-gate IC's</b>," <i>Electronics</i> (29 Sept 1969) pp. 88-89.<br><br />
Faggin, F. and Hoff, M.E. "<b>Standard parts and custom design merge in four-chip processor kit</b>," <i>Electronics</i> (24 April 1972) pp. 112-116.<br><br />
Altman, Laurence "<b>Single Chip Microprocessors open up a New World of Applications</b>," <i>Electronics</i> (18 April 1974) pp. 81-87.<br><br />
Noyce, R., and Hoff, M. "<b>A History of Microprocessor Development at Intel</b>," <i>IEEE Micro</i>, Vol. 1, No. 1 (1981) pp. 8-21.<br><br />
Faggin, F.; Hoff, M.E., Jr.; Mazor, S.; Shima, M. "<b>The history of the 4004</b>," <i>IEEE Micro</i>, Vol. 16, Issue 6 (December 1996) pp. 10-20.<br><br />
Faggin, F., Shima, M., Hoff, M.E., Feeny, H., Mazor S. "<b>The MCS4 - An LSI micro-computer system</b>," IEEE 1972 Region Six Conference, IEEE Press (1972) pp. 8-11.<br><br />
<b>[[Media:Ref2-Intel MCS-4 DataSheet.pdf|Intel MCS-4 Micro Computer Set</b> Data Sheet, 1971 (12 pages).]]<br><br />
[[Media:Ref3-AugartenBookExcerpt.pdf|Augarten, Stan. "<b>The First Microprocessor - 4004</b>,"]] <i>State Of The Art: A Photographic History of the Integrated Circuit</i>, New Haven & New York: Ticknor and Fields, 1983, pp. 30-31.<br><br />
Malone, Michael S. "<b><i>The Microprocessor: A Biography</i></b>," New York: Springer-Verlag TELOS, 1995, pp. 3-20.<br><br />
<br><br />
4. INTERVIEWS & ORAL HISTORIES<br><br />
[https://ethw.org/Oral-History:Federico_Faggin <b>Federico Faggin: An Interview Conducted by John Vardalas</b>, IEEE History Center Interview #442, 27 May 2004].<br><br />
[https://archive.computerhistory.org/resources/access/text/2012/07/102658025-05-01-acc.pdf <b>Federico Faggin Oral History</b>, interviewed by Gardner Hendrie (22 Sept 2004, 13 Dec 2004 and 3 March 2005), Computer History Museum Catalog # 102658025 ].<br><br />
[https://archive.computerhistory.org/resources/access/text/2012/08/102657974-05-01-acc.pdf <b>Ted Hoff and Stan Mazor on their contributions to the Intel 4004</b>, Ted Hoff and Stan Mazor interviewed by David Laws (20 Sept 2006), Computer History Museum Catalog #102657974 ]<br><br />
[https://archive.computerhistory.org/resources/access/text/2012/04/102658187-05-01-acc.pdf <b>Oral History Panel on the Development and Promotion of the Intel 4004 Microprocessor</b>, Federico Faggin, Hal Feeney, Ted Hoff, Stan Mazor and Masatoshi Shima, interviewed by Dave House, and edited by David Laws (25 April 2007), Computer History Museum Catalog #102658187 ]<br><br />
<br><br />
5. ONLINE VIDEOS<br><br />
[https://www.youtube.com/watch?v=y0TPWoJGv-E <b>The Designer Behind the First Microprocessor: Federico Faggin</b> ] (length: 4:19)<br><br />
[https://www.youtube.com/watch?v=7MgHsgoilQ4 <b>Ted Hoff, Inventor of the Microprocessor</b>, Richard Newton Distinguished Innovator Lecture Series, U.C. Berkeley (8 Sept 2009) ] (length: 48:08)<br><br />
[https://www.youtube.com/watch?v=j00AULJLCNo <b>Intel 4004 Microprocessor 35th Anniversary</b>, Computer History Museum (13 Nov 2006) ] (length: 1:37:59)<br><br />
'''[https://www.computerhistory.org/revolution/digital-logic/12/285/2285 The Story of the Intel 4004]''', Computer History Museum: Collection of video excerpts of Ted Hoff, Masatoshi Shima, Stan Mazor, Federico Faggin and Dave House (3:08) <br><br />
'''[https://youtu.be/k_zl4AhPtz0 Intel Presents "The MCS-4 Story]":''' Abbreviated version of an Intel video shown as a 16mm film at seminars across the U.S.; narrated by Ted Hoff, with video assistance by Stan Mazor; the full version included technical details such as how a 4004 jump instruction was fetched and executed (2:19)<br><br />
<br><br />
6. BLOG, PHOTOS & MISC. DOCUMENTS<br><br />
[https://computerhistory.org/blog/who-invented-the-microprocessor/ <b>Who Invented the Microprocessor?</b>, David Laws (20 Sept 2018) ].<br><br />
[https://newsroom.intel.com/editorials/intel-a-look-back-on-the-early-years/ <b>Intel: A Look Back on the Early Years</b>: Photos from Intel in the Early 1970s ].<br><br />
[https://www.intel.com/content/www/us/en/history/history-1988-annual-report.html <b>Intel 1988 Annual Report</b>: Includes historical outline and photos from Intel's first 20 years ].<br><br />
[https://www.computerhistory.org/collections/catalog/102635152 <b>Photo of 4004 die</b> ].<br><br />
[https://www.computerhistory.org/siliconengine/microprocessor-integrates-cpu-function-onto-a-single-chip/ <b>1971: Microprocessor Integrates CPU Function on to a Single Chip - Silicon-Gate Process Technology and Design Advances Squeeze Computer Central Processing Units (CPU) Onto Single Chips</b>, <i>The Silicon Engine</i> (30 May 2020) (includes a plethora of links, photos and citations related to the 4004, along with a nice overview) ].<br><br />
[https://www.intel-vintage.info/apps/blog/ <b>Unofficial Intel Archives Website</b>: photos, annual reports, software, documentation, etc. ].<br><br />
[https://www.computerhistory.org/revolution/digital-logic/12/285/1534 '''Busicom 141-PF Printing Calculator Engineering Prototype, 1971'''], Computer History Museum: Engineering prototype of the successful test bed for the first commercial application of the Intel 4004<br />
<br><br />
7. VIDEODISC<br><br />
[https://searchworks.stanford.edu/view/6964777 <b>The Microprocessor Chronicles: The History of the Microprocessor</b> "The history of the invention of the microprocessors through three and half decades of technological change as told by those that made it happen. Interviews with Dennis Carter, Federico Faggin, John Hennessy, Ted Hoff, Dave House, Stan Mazor, Regis McKenna, Gordon Moore, Jerrt Sanders, Albert Yu," Stanford University Library; Palo Alto, CA, 2005 ]<br />
|submitted=Yes<br />
}}</div>Administrator1http://ieeemilestones.ethw.org/index.php?title=Milestone-Proposal:Intel_4004_Microprocessor&diff=9569Milestone-Proposal:Intel 4004 Microprocessor2020-10-12T19:38:30Z<p>Administrator1: </p>
<hr />
<div>{{Proposal<br />
|docketid=2020-04<br />
|litigation=No<br />
|more than 25 years=Yes<br />
|within fields of interest=Yes<br />
|benefit to humanity=Yes<br />
|regional importance=Yes<br />
|ou is paying=Yes<br />
|ou is arranging dedication=Yes<br />
|section is taking responsibility for plaque=Yes<br />
|a11=Yes<br />
|a3=1971<br />
|a1=Intel 4004 Microprocessor, 1971<br />
|plaque citation=The Intel 4004 microprocessor incorporated a 4-bit computer's Central Processing Unit (CPU). Its new silicon-gate MOS fabrication enabled a single-chip design with significant cost and performance improvements over existing multi-chip designs. Although initially created for a family of calculating machines, its general-purpose instruction set allowed software customization. The single-chip 4004 created the industry model for the microprocessor — a key driver of the digital information age.<br />
|a2b=Santa Clara Valley<br />
|IEEE units paying={{IEEE Organizational Unit Paying<br />
|Unit=Santa Clara Valley<br />
|Senior officer name=Taylor Winship<br />
|Senior officer email=taylor_winship@att.net<br />
}}<br />
|IEEE units arranging={{IEEE Organizational Unit Arranging<br />
|Unit=Santa Clara Valley<br />
|Senior officer name=Taylor Winship<br />
|Senior officer email=taylor_winship@att.net<br />
}}<br />
|IEEE sections monitoring={{IEEE Section Monitoring<br />
|Section=Santa Clara Valley<br />
|Section chair name=Tayor Winship<br />
|Section chair email=taylor_winship@att.net<br />
}}<br />
|Milestone proposers={{Milestone proposer<br />
|Proposer name=David Laws<br />
|Proposer email=laws@computerhistory.org<br />
}}{{Milestone proposer<br />
|Proposer name=Brian Berg<br />
|Proposer email=brianberg@gmail.com<br />
}}<br />
|a2a=Robert N. Noyce Building (Intel's Headquarters), 2200 Mission College Blvd, Santa Clara, CA 95054 USA 37.3882663, -121.9637798<br />
|a7=By the entrance to the Intel Museum, which is accessible from the ground floor lobby of the Robert N. Noyce Building (Intel's Headquarters).<br />
|a8=The 4004 development work was performed at Intel's original headquarters at 365 E. Middlefield Rd., Mountain View, CA, which is not extant. The engineering design team moved to Intel's new headquarters at 3065 Bowers Ave., Santa Clara, CA (later called Santa Clara 1, or "SC1") in 1971, prior to the November 1971 product launch. This left only the Fab 1 facility in Mountain View, where the MCS-4 Micro Computer Chip Set was manufactured for at least its first year of production. SC1 is extant and retains the SC1 designation, is no longer Intel's Headquarters, and is not accessible to the public. SC1 is 2.1 miles from the Intel Museum site.<br />
|mounting details=Indoors in a location adjoining the Intel Museum's entrance.<br />
|a9=The Intel Museum is open to the public during normal business hours. There is no charge for entry.<br />
|a10=Intel Corporation<br />
|a4=The Intel 4004 was a complete 4-bit parallel central processing unit (CPU) on a single silicon chip. Introduced in 1971 as a member of the MCS-4 Micro Computer Chip Set, it was the first commercial microprocessor integrated circuit offered to the general public. The success of the product established the commercial viability of the microprocessor concept, led to the development of 8-bit chips from Intel and other vendors, and also led to the use of microprocessors first in embedded products, personal computers, and then throughout the industry. Single-chip microprocessors are now ubiquitous throughout the world.<br><br />
<br><br />
Development work began in 1969 when Japanese calculator-maker Busicom asked Intel to design a set of chips for a family of calculating machines. The original design called for seven custom chips, out of which small computers based on ROM and shift register read-write memory could be built. Three of the seven chips were intended to perform the function of a CPU optimized for a variety of calculating machines. Ted Hoff saw the opportunity to simplify this approach by using dynamic RAM memory then in development at Intel. His proposed solution was an architecture for a single-chip, general-purpose CPU and three companion chips for memory and I/O.<br><br />
<br><br />
As described in the [https://www.computerhistory.org/siliconengine/silicon-gate-technology-developed-for-ics/ Computer History Museum's 1968: SILICON GATE TECHNOLOGY DEVELOPED FOR ICS webpage], Federico Faggin developed enhancements to MOS technology that allowed the general-purpose processor that was being developed under contract to Busicom to be miniaturized enough so as to fit onto a single chip: "Intel pursued silicon-gate as the primary technology for semiconductor memories as it delivered 3 to 5 times faster speed in half the chip area of conventional MOS. Intel's first commercial MOS device, the 1101 256-bit RAM, was introduced in 1969. Faggin joined Intel in 1970. By adding a buried contact and other process enhancements for logic applications he was able to design the 4004 microprocessor CPU to fit on a manufacturable die size." This is further described in the [https://www.computerhistory.org/siliconengine/microprocessor-integrates-cpu-function-onto-a-single-chip/ Computer History Museum's 1971: MICROPROCESSOR INTEGRATES CPU FUNCTION ONTO A SINGLE CHIP webpage].<br><br />
<br><br />
Cognizant of financial troubles at Busicom, and sensing the market potential of the product, Intel made what was perhaps the most important decision in the history of the company: they returned their $60,000 design fee to Busicom and agreed to sell them the chip set at a lower cost in exchange for Busicom's surrendering of its exclusive rights. Now with its complete ownership, Intel introduced the chip set to the world in November 1971 with an advertisement that touted "Announcing a new era of integrated electronics: A micro-programmable computer on a chip!"<br><br />
<br><br />
Because electronic designers had never before had the ability to design a new compact computerized product with such a small set of chips while using software to quickly tailor and fine-tune its capabilities, an extensive campaign to educate the engineering community about the MCS-4 chip family was necessary. An important part of the campaign included educating engineers about the software since this was a requirement that was new for a hardware engineering team. In addition, as no high-level language compilers were available for the 4004 chip, the software needed to be written in assembly language. After a slow start, the chip family began to find a home in control applications that included traffic lights and taxi meters. While these initial usages were relatively unsophisticated, they had a small footprint, were created at a low cost, and could be easily tweaked with software - and they were the start of a new realm of computerized products.<br />
|a6=The key technical obstacle was adapting Intel's P-channel silicon-gate MOS process to accommodate 2300 transistors in a chip size that was economical and practical to manufacture in volume. As discussed with reference to Federico Faggin in the [[Media:Ref1-Electronics MOS-Story(29-Sept-1969).pdf|29 Sept 1969 issue of <i>Electronics</i>]], the new direction in MOS technology at that time was the development of a self-aligned gate MOS process (to reduce parasitic capacitances) combined with a lower power supply voltage (from -24 volts to -15 volts) by reducing the maximum threshold voltage from -9 volts to -3.5 volts. This was accomplished for the first time in 1968 by using polysilicon instead of aluminum in the gate electrode. The result was a technology that, for the same power dissipation, resulted in (1) a 5x speed improvement, (2) reduced leakage current (by more than 100 times), (3) higher circuit density (especially for random logic designs) using the buried contact, which allowed fabricating an insulated contact between junctions and polysilicon, thereby resulting in half the chip area for the same function, and (4) higher reliability by using phosphorus gettering to reduce metal impurities, which was not possible with an aluminum gate. This increase in speed and functionality within a single chip allowed the 4004 to be a single-chip CPU, with a resultant improved cost and greatly improved performance, as compared with a multi-chip implementation.<br><br />
<br><br />
The MCS-4 family consisted of: 4001 (ROM), 4002 (RAM), 4003 (Shift Register) and 4004 (CPU), and each device had a pin count of only 16. While this low pin count reduced manufacturing cost, it also necessitated a cumbersome 4-bit bi-directional data bus for the communication of 12-bit addresses and 8-bit instructions amongst these 4 devices, a scheme implemented using time-division multiplexing and a fixed 8-click time clock in which each of the 8 clicks had an agreed direction and purpose, and as further described in [https://patentimages.storage.googleapis.com/7e/e8/25/605e0d53b55b6c/US3821715.pdf U.S. Patent 3,821,715]. While performance thereby suffered by a factor of 2.5, the 5x speed and 2x size improvements enabled by the use of silicon-gate MOS technology (which also allowed the chip to be small enough to fit into a 16-pin package) resulted in a family of devices whose overall system functionality was not impaired. A similar approach was applied to the 18-pin 8008 (introduced in 1972), sacrificing speed and requiring 35 external ICs to interface the chip to memory and I/O. Using a 40-pin package, Intel's highly successful 8080 microprocessor finally replaced the 8008 in 1974.<br><br />
<br><br />
The political and commercial obstacles at the time included initial reluctance by Intel management to promote a chip that would compete with products from the company’s existing customers, the reluctance of the market to grasp the power inherent in a single-chip CPU, and the lack of knowledge regarding how to use such a device. The latter two obstacles were overcome by way of extensive customer education programs, and new hardware and software development tools.<br />
|a5=By the late 1960s, designers were striving to integrate the CPU functions of a computer onto a handful of MOS LSI chips. Two notable examples are (1) in 1969, Lee Boysel created the Four-Phase Systems Inc. AL-1, an 8-bit CPU slice that was expandable to 32 bits, and (2) in 1970, Steve Geller and Ray Holt of Garrett AiResearch designed the MP944 20-bit chip set to implement the F-14A Central Air Data Computer on six chips. Both were multi-chip custom designs for specific applications.<br><br />
<br><br />
David Laws, Semiconductor Curator at the Computer History Museum, wrote a 2018 essay titled [https://computerhistory.org/blog/who-invented-the-microprocessor/ Who Invented the Microprocessor?] in which he states "This article describes a chronology of early approaches to integrating the primary building blocks of a computer on to fewer and fewer microelectronic chips, culminating in the concept of the microprocessor." His treatise describes how the single-chip 4004 microprocessor was preceded by a number of other devices that incorporated variations of a microprocessor device, but which were all multi-chip implementations.<br><br />
<br><br />
The Intel 4004 was a general-purpose device that integrated more of the essential logical elements of a processor onto a single chip than what had been done previously. These functions included a program counter, instruction decode/control logic, the ALU, data registers, and the data path between these elements. Although originally designed to implement a family of programmable calculating machines by way of Intel's contract with the Japanese company Busicom, the 4004's general-purpose instruction set allowed it to be embedded in devices such as peripherals, terminals, process controllers, and test and measurement systems.<br />
|references=1. HONORS<br><br />
[https://marconisociety.org/fellows/federico-faggin/ The Marconi Society's 1988 <b>Marconi Prize</b> to Federico Faggin "for his pioneering contributions to the implementation of the microprocessor, a principal building block of modern telecommunications" ].<br><br />
The 1988 <b>Gold Medal for Science and Technology</b> to Federico Faggin from the Italian Prime Minister.<br><br />
[https://www.computer.org/profiles/federico-faggin The 1994 IEEE Computer Society's <b>W. Wallace McDowell Award</b> to Federico Faggin “for the development of the Silicon Gate Process, and the first commercial microprocessor” ].<br><br />
[https://www.invent.org/inductees/federico-faggin The 1996 <b>National Inventors Hall of Fame</b> inductees included Federico Faggin], [https://www.invent.org/inductees/marcian-e-ted-hoff Marcian E. (Ted) Hoff] and [https://www.invent.org/inductees/stanley-mazor Stanley Mazor, for the microprocessor].<br><br />
The 1997 <b>Kyoto Prize</b> recipients included [https://www.kyotoprize.org/en/laureates/federico_faggin/ Federico Faggin], [https://www.kyotoprize.org/en/laureates/marcian_edward_hoff_jr/ Marcian Edward Hoff, Jr. ], [https://www.kyotoprize.org/en/laureates/stanley_mazor/ Stanley Mazor] and [https://www.kyotoprize.org/en/laureates/masatoshi_shima/ Masatoshi Shima] in Advanced Technology: Electronics.<br><br />
[https://www.semiconductors.org/news-events/awards/ The 2000 <b>Robert N. Noyce Award</b> presented by the Semiconductor Industry Association to Federico Faggin, Stanley Mazor and Ted Hoff, "Inventors of the Microprocessor" ].<br><br />
[https://computerhistory.org/press-releases/2009-Fellow-Awards-Honorees/ The 2009 <b>Computer History Museum Fellows</b> included Federico Faggin, Marcian Edward "Ted" Hoff, Stan Mazor and Masatoshi Shima "for their work on the Intel 4004, the world’s first commercial microprocessor" ].<br><br />
The 2009 <b>National Medal of Technology and Innovation</b> recipients [https://www.uspto.gov/learning-and-resources/ip-programs-and-awards/national-medal-technology-and-innovation/recipients/2009 included Federico Faggin, Marcian E. Hoff, Jr. and Stanley Mazor, as presented by President Obama] "for the conception, design and application of the first microprocessor, which was commercially adopted and became the universal building block of digital electronic systems, significantly impacting the global economy and people's day-to-day lives".<br><br />
<br><br />
2. PATENTS RESULTING FROM 4004 DESIGN<br><br />
[https://patentimages.storage.googleapis.com/6b/d7/16/e26a04b80c6eb6/US3753011.pdf Faggin, F. “<b>Power supply settable bi-stable circuit</b>” U.S. Patent 3,753,011 ]<br><br />
[https://patentimages.storage.googleapis.com/7e/e8/25/605e0d53b55b6c/US3821715.pdf Hoff, Jr., M. E.; Mazor, Stanley; Faggin, Federico. "<b>Memory System for a Multi-Chip Digital Computer</b>" U.S. Patent 3,821,715 ]<br><br />
<br><br />
3. TECHNICAL ARTICLES, CONFERENCE PAPERS & BOOKS<br><br />
"<b>A faster generation of MOS devices with low thresholds is riding the crest of the new wave, silicon-gate IC's</b>," <i>Electronics</i> (29 Sept 1969) pp. 88-89.<br><br />
Faggin, F. and Hoff, M.E. "<b>Standard parts and custom design merge in four-chip processor kit</b>," <i>Electronics</i> (24 April 1972) pp. 112-116.<br><br />
Altman, Laurence "<b>Single Chip Microprocessors open up a New World of Applications</b>," <i>Electronics</i> (18 April 1974) pp. 81-87.<br><br />
Noyce, R., and Hoff, M. "<b>A History of Microprocessor Development at Intel</b>," <i>IEEE Micro</i>, Vol. 1, No. 1 (1981) pp. 8-21.<br><br />
Faggin, F.; Hoff, M.E., Jr.; Mazor, S.; Shima, M. "<b>The history of the 4004</b>," <i>IEEE Micro</i>, Vol. 16, Issue 6 (December 1996) pp. 10-20.<br><br />
Faggin, F., Shima, M., Hoff, M.E., Feeny, H., Mazor S. "<b>The MCS4 - An LSI micro-computer system</b>," IEEE 1972 Region Six Conference, IEEE Press (1972) pp. 8-11.<br><br />
<b>[[Media:Ref2-Intel MCS-4 DataSheet.pdf|Intel MCS-4 Micro Computer Set</b> Data Sheet, 1971 (12 pages).]]<br><br />
[[Media:Ref3-AugartenBookExcerpt.pdf|Augarten, Stan. "<b>The First Microprocessor - 4004</b>,"]] <i>State Of The Art: A Photographic History of the Integrated Circuit</i>, New Haven & New York: Ticknor and Fields, 1983, pp. 30-31.<br><br />
Malone, Michael S. "<b><i>The Microprocessor: A Biography</i></b>," New York: Springer-Verlag TELOS, 1995, pp. 3-20.<br><br />
<br><br />
4. INTERVIEWS & ORAL HISTORIES<br><br />
[https://ethw.org/Oral-History:Federico_Faggin <b>Federico Faggin: An Interview Conducted by John Vardalas</b>, IEEE History Center Interview #442, 27 May 2004].<br><br />
[https://archive.computerhistory.org/resources/access/text/2012/07/102658025-05-01-acc.pdf <b>Federico Faggin Oral History</b>, interviewed by Gardner Hendrie (22 Sept 2004, 13 Dec 2004 and 3 March 2005), Computer History Museum Catalog # 102658025 ].<br><br />
[https://archive.computerhistory.org/resources/access/text/2012/08/102657974-05-01-acc.pdf <b>Ted Hoff and Stan Mazor on their contributions to the Intel 4004</b>, Ted Hoff and Stan Mazor interviewed by David Laws (20 Sept 2006), Computer History Museum Catalog #102657974 ]<br><br />
[https://archive.computerhistory.org/resources/access/text/2012/04/102658187-05-01-acc.pdf <b>Oral History Panel on the Development and Promotion of the Intel 4004 Microprocessor</b>, Federico Faggin, Hal Feeney, Ted Hoff, Stan Mazor and Masatoshi Shima, interviewed by Dave House, and edited by David Laws (25 April 2007), Computer History Museum Catalog #102658187 ]<br><br />
<br><br />
5. ONLINE VIDEOS<br><br />
[https://www.youtube.com/watch?v=y0TPWoJGv-E <b>The Designer Behind the First Microprocessor: Federico Faggin</b> ] (length: 4:19)<br><br />
[https://www.youtube.com/watch?v=7MgHsgoilQ4 <b>Ted Hoff, Inventor of the Microprocessor</b>, Richard Newton Distinguished Innovator Lecture Series, U.C. Berkeley (8 Sept 2009) ] (length: 48:08)<br><br />
[https://www.youtube.com/watch?v=j00AULJLCNo <b>Intel 4004 Microprocessor 35th Anniversary</b>, Computer History Museum (13 Nov 2006) ] (length: 1:37:59)<br><br />
<br><br />
'''[https://www.computerhistory.org/revolution/digital-logic/12/285/2285 The Story of the Intel 4004]''', Computer History Museum: Collection of video excerpts of Ted Hoff, Masatoshi Shima, Stan Mazor, Federico Faggin and Dave House (3:08) <br><br />
<br><br />
'''[https://youtu.be/k_zl4AhPtz0 Intel Presents "The MCS-4 Story]":''' Abbreviated version of an Intel video shown as a 16mm film at seminars across the U.S.; narrated by Ted Hoff, with video assistance by Stan Mazor; the full version included technical details such as how a 4004 jump instruction was fetched and executed (2:19)<br><br />
<br><br />
6. BLOG, PHOTOS & MISC. DOCUMENTS<br><br />
[https://computerhistory.org/blog/who-invented-the-microprocessor/ <b>Who Invented the Microprocessor?</b>, David Laws (20 Sept 2018) ].<br><br />
[https://newsroom.intel.com/editorials/intel-a-look-back-on-the-early-years/ <b>Intel: A Look Back on the Early Years</b>: Photos from Intel in the Early 1970s ].<br><br />
[https://www.intel.com/content/www/us/en/history/history-1988-annual-report.html <b>Intel 1988 Annual Report</b>: Includes historical outline and photos from Intel's first 20 years ].<br><br />
[https://www.computerhistory.org/collections/catalog/102635152 <b>Photo of 4004 die</b> ].<br><br />
[https://www.computerhistory.org/siliconengine/microprocessor-integrates-cpu-function-onto-a-single-chip/ <b>1971: Microprocessor Integrates CPU Function on to a Single Chip - Silicon-Gate Process Technology and Design Advances Squeeze Computer Central Processing Units (CPU) Onto Single Chips</b>, <i>The Silicon Engine</i> (30 May 2020) (includes a plethora of links, photos and citations related to the 4004, along with a nice overview) ].<br><br />
[https://www.intel-vintage.info/apps/blog/ <b>Unofficial Intel Archives Website</b>: photos, annual reports, software, documentation, etc. ].<br><br />
[https://www.computerhistory.org/revolution/digital-logic/12/285/1534 '''Busicom 141-PF Printing Calculator Engineering Prototype, 1971'''], Computer History Museum: Engineering prototype of the successful test bed for the first commercial application of the Intel 4004<br />
<br><br />
<br><br />
7. VIDEODISC<br><br />
[https://searchworks.stanford.edu/view/6964777 <b>The Microprocessor Chronicles: The History of the Microprocessor</b> "The history of the invention of the microprocessors through three and half decades of technological change as told by those that made it happen. Interviews with Dennis Carter, Federico Faggin, John Hennessy, Ted Hoff, Dave House, Stan Mazor, Regis McKenna, Gordon Moore, Jerrt Sanders, Albert Yu," Stanford University Library; Palo Alto, CA, 2005 ]<br />
|submitted=Yes<br />
}}</div>Administrator1http://ieeemilestones.ethw.org/index.php?title=Template:IEEE_Organizational_Unit_Arranging&diff=9545Template:IEEE Organizational Unit Arranging2020-10-05T13:17:16Z<p>Administrator1: </p>
<hr />
<div><noinclude><br />
This is the "IEEE Organizational Unit Paying" template.<br />
</noinclude><includeonly><br />
'''Unit:''' {{{Unit}}}<br /><br />
'''Senior Officer Name:''' {{{Senior officer name}}}<br />
</includeonly></div>Administrator1http://ieeemilestones.ethw.org/index.php?title=Template:IEEE_Organizational_Unit_Paying&diff=9544Template:IEEE Organizational Unit Paying2020-10-05T13:17:14Z<p>Administrator1: </p>
<hr />
<div><noinclude><br />
This is the "IEEE Organizational Unit Paying" template.<br />
</noinclude><includeonly><br />
'''Unit:''' {{{Unit}}}<br /><br />
'''Senior Officer Name:''' {{{Senior officer name}}}<br />
</includeonly></div>Administrator1http://ieeemilestones.ethw.org/index.php?title=Template:IEEE_Section_Monitoring&diff=9543Template:IEEE Section Monitoring2020-10-05T13:17:12Z<p>Administrator1: </p>
<hr />
<div><noinclude><br />
This is the "IEEE Section Monitoring" template.<br />
</noinclude><includeonly><br />
'''IEEE Section:''' {{{Section|}}}<br /><br />
'''IEEE Section Chair name:''' {{{Section chair name}}}<br />
</includeonly></div>Administrator1http://ieeemilestones.ethw.org/index.php?title=Template:Milestone_proposer&diff=9542Template:Milestone proposer2020-10-05T13:15:00Z<p>Administrator1: </p>
<hr />
<div><noinclude><br />
This is the "Milestone proposer" template.<br />
</noinclude><includeonly><br />
'''Proposer name:''' {{{Proposer name}}}<br /><br />
'''Proposer email:''' {{{field|''Proposer's email masked to public''}}}<br />
</includeonly></div>Administrator1